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141 lines
3.3 KiB
ArmAsm
141 lines
3.3 KiB
ArmAsm
/*
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* NEON code contributed by Siarhei Siamashka <siarhei.siamashka@nokia.com>.
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* Origin: http://sourceware.org/ml/libc-ports/2009-07/msg00003.html
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*
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* The GNU C Library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public License.
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*
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* Tweaked for Android by Jim Huang <jserv@0xlab.org>
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*/
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.arm
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.fpu neon
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@ void* memcpy(void *destination, const void *source, size_t num)
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.global memcpy_neon
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/*
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* ENABLE_UNALIGNED_MEM_ACCESSES macro can be defined to permit the use
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* of unaligned load/store memory accesses supported since ARMv6. This
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* will further improve performance, but can purely theoretically cause
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* problems if somebody decides to set SCTLR.A bit in the OS kernel
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* (to trap each unaligned memory access) or somehow mess with strongly
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* ordered/device memory.
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*/
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#define ENABLE_UNALIGNED_MEM_ACCESSES 1
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#define NEON_MAX_PREFETCH_DISTANCE 320
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.align 4
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memcpy_neon:
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.fnstart
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mov ip, r0
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cmp r2, #16
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blt 4f @ Have less than 16 bytes to copy
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@ First ensure 16 byte alignment for the destination buffer
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tst r0, #0xF
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beq 2f
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tst r0, #1
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ldrneb r3, [r1], #1
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strneb r3, [ip], #1
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subne r2, r2, #1
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tst ip, #2
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#ifdef ENABLE_UNALIGNED_MEM_ACCESSES
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ldrneh r3, [r1], #2
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strneh r3, [ip], #2
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#else
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ldrneb r3, [r1], #1
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strneb r3, [ip], #1
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ldrneb r3, [r1], #1
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strneb r3, [ip], #1
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#endif
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subne r2, r2, #2
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tst ip, #4
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beq 1f
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vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]!
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vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [ip, :32]!
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sub r2, r2, #4
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1:
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tst ip, #8
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beq 2f
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vld1.8 {d0}, [r1]!
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vst1.8 {d0}, [ip, :64]!
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sub r2, r2, #8
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2:
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subs r2, r2, #32
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blt 3f
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mov r3, #32
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@ Main copy loop, 32 bytes are processed per iteration.
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@ ARM instructions are used for doing fine-grained prefetch,
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@ increasing prefetch distance progressively up to
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@ NEON_MAX_PREFETCH_DISTANCE at runtime
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1:
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vld1.8 {d0-d3}, [r1]!
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cmp r3, #(NEON_MAX_PREFETCH_DISTANCE - 32)
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pld [r1, r3]
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addle r3, r3, #32
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vst1.8 {d0-d3}, [ip, :128]!
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sub r2, r2, #32
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cmp r2, r3
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bge 1b
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cmp r2, #0
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blt 3f
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1: @ Copy the remaining part of the buffer (already prefetched)
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vld1.8 {d0-d3}, [r1]!
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subs r2, r2, #32
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vst1.8 {d0-d3}, [ip, :128]!
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bge 1b
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3: @ Copy up to 31 remaining bytes
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tst r2, #16
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beq 4f
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vld1.8 {d0, d1}, [r1]!
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vst1.8 {d0, d1}, [ip, :128]!
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4:
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@ Use ARM instructions exclusively for the final trailing part
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@ not fully fitting into full 16 byte aligned block in order
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@ to avoid "ARM store after NEON store" hazard. Also NEON
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@ pipeline will be (mostly) flushed by the time when the
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@ control returns to the caller, making the use of NEON mostly
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@ transparent (and avoiding hazards in the caller code)
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#ifdef ENABLE_UNALIGNED_MEM_ACCESSES
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movs r3, r2, lsl #29
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ldrcs r3, [r1], #4
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strcs r3, [ip], #4
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ldrcs r3, [r1], #4
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strcs r3, [ip], #4
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ldrmi r3, [r1], #4
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strmi r3, [ip], #4
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movs r2, r2, lsl #31
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ldrcsh r3, [r1], #2
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strcsh r3, [ip], #2
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ldrmib r3, [r1], #1
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strmib r3, [ip], #1
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#else
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movs r3, r2, lsl #29
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bcc 1f
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.rept 8
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ldrcsb r3, [r1], #1
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strcsb r3, [ip], #1
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.endr
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1:
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bpl 1f
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.rept 4
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ldrmib r3, [r1], #1
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strmib r3, [ip], #1
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.endr
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1:
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movs r2, r2, lsl #31
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ldrcsb r3, [r1], #1
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strcsb r3, [ip], #1
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ldrcsb r3, [r1], #1
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strcsb r3, [ip], #1
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ldrmib r3, [r1], #1
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strmib r3, [ip], #1
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#endif
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bx lr
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.fnend
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