mirror of
https://github.com/CTCaer/switch-l4t-atf.git
synced 2024-11-30 13:20:22 +00:00
Merge changes I2c9aecc9,Ie6a019f4,Ief6f0a63,Iec9c80f2 into integration
* changes: fdts: stm32mp1: add support for the Seeed Odyssey SoM and board fdts: stm32mp1: add alternative SDMMC2 pins to the pinctrl fdts: stm32mp1: add I2C2 pins in the pinctrl fdts: stm32mp1: add the I2C2 peripheral in the SoC DTS
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
067cb3aedf
@ -31,6 +31,16 @@
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};
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};
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i2c2_pins_a: i2c2-0 {
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pins {
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pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
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<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
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bias-disable;
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drive-open-drain;
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slew-rate = <0>;
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};
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};
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qspi_clk_pins_a: qspi-clk-0 {
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pins {
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pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
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@ -166,6 +176,15 @@
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};
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};
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sdmmc2_d47_pins_d: sdmmc2-d47-3 {
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pins {
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pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
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<STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
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<STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
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<STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
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};
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};
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uart4_pins_a: uart4-0 {
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pins1 {
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pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
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@ -121,6 +121,21 @@
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status = "disabled";
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};
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i2c2: i2c@40013000 {
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compatible = "st,stm32mp15-i2c";
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reg = <0x40013000 0x400>;
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interrupt-names = "event", "error";
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interrupts = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
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<&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc I2C2_K>;
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resets = <&rcc I2C2_R>;
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#address-cells = <1>;
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#size-cells = <0>;
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st,syscfg-fmp = <&syscfg 0x4 0x2>;
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wakeup-source;
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status = "disabled";
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};
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uart7: serial@40018000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40018000 0x400>;
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325
fdts/stm32mp157c-odyssey-som.dtsi
Normal file
325
fdts/stm32mp157c-odyssey-som.dtsi
Normal file
@ -0,0 +1,325 @@
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/*
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* Copyright (C) 2019, STMicroelectronics. All Rights Reserved.
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* Copyright (C) 2021, Grzegorz Szymaszek.
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*
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* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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*/
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#include "stm32mp157.dtsi"
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#include "stm32mp15xc.dtsi"
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#include "stm32mp15-pinctrl.dtsi"
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#include "stm32mp15xxac-pinctrl.dtsi"
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
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/ {
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memory@c0000000 {
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device_type = "memory";
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reg = <0xc0000000 0x20000000>;
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};
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vin: vin {
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compatible = "regulator-fixed";
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regulator-name = "vin";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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};
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&bsec {
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board_id: board_id@ec {
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reg = <0xec 0x4>;
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st,non-secure-otp;
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};
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};
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&clk_hse {
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st,digbypass;
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};
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&cpu0 {
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cpu-supply = <&vddcore>;
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};
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&cpu1 {
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cpu-supply = <&vddcore>;
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};
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&cryp1 {
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status = "okay";
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};
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&hash1 {
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_pins_a>;
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clock-frequency = <400000>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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pmic: stpmic@33 {
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compatible = "st,stpmic1";
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reg = <0x33>;
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interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "okay";
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regulators {
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compatible = "st,stpmic1-regulators";
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buck1-supply = <&vin>;
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buck2-supply = <&vin>;
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buck3-supply = <&vin>;
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buck4-supply = <&vin>;
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ldo1-supply = <&v3v3>;
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ldo2-supply = <&vin>;
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ldo3-supply = <&vdd_ddr>;
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ldo4-supply = <&vin>;
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ldo5-supply = <&vin>;
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ldo6-supply = <&v3v3>;
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vref_ddr-supply = <&vin>;
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boost-supply = <&vin>;
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pwr_sw1-supply = <&bst_out>;
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pwr_sw2-supply = <&bst_out>;
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vddcore: buck1 {
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regulator-name = "vddcore";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd_ddr: buck2 {
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regulator-name = "vdd_ddr";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd: buck3 {
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regulator-name = "vdd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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st,mask-reset;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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v3v3: buck4 {
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regulator-name = "v3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-over-current-protection;
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regulator-initial-mode = <0>;
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};
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v1v8_audio: ldo1 {
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regulator-name = "v1v8_audio";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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v3v3_hdmi: ldo2 {
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regulator-name = "v3v3_hdmi";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vtt_ddr: ldo3 {
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regulator-name = "vtt_ddr";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <750000>;
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regulator-always-on;
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regulator-over-current-protection;
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};
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vdd_usb: ldo4 {
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regulator-name = "vdd_usb";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vdda: ldo5 {
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regulator-name = "vdda";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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regulator-boot-on;
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};
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v1v2_hdmi: ldo6 {
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regulator-name = "v1v2_hdmi";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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};
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vref_ddr: vref_ddr {
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regulator-name = "vref_ddr";
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regulator-always-on;
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regulator-over-current-protection;
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};
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bst_out: boost {
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regulator-name = "bst_out";
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};
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vbus_otg: pwr_sw1 {
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regulator-name = "vbus_otg";
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};
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vbus_sw: pwr_sw2 {
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regulator-name = "vbus_sw";
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regulator-active-discharge = <1>;
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};
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};
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pmic_watchdog: watchdog {
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compatible = "st,stpmic1-wdt";
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status = "disabled";
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};
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};
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};
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&iwdg2 {
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timeout-sec = <32>;
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status = "okay";
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};
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&pwr_regulators {
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vdd-supply = <&vdd>;
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vdd_3v3_usbfs-supply = <&vdd_usb>;
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};
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&rcc {
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secure-status = "disabled";
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_MCU_PLL3P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_PLL4P
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL4P
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSE
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4R
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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CLK_SAI4_PLL3Q
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CLK_RNG1_LSI
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CLK_RNG2_LSI
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CLK_LPTIM1_PCLK1
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CLK_LPTIM23_PCLK3
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CLK_LPTIM45_LSE
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>;
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/* VCO = 1300.0 MHz => P = 650 (CPU) */
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pll1: st,pll@0 {
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compatible = "st,stm32mp1-pll";
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reg = <0>;
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cfg = <2 80 0 0 0 PQR(1,0,0)>;
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frac = <0x800>;
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};
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
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pll2: st,pll@1 {
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compatible = "st,stm32mp1-pll";
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reg = <1>;
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cfg = <2 65 1 0 0 PQR(1,1,1)>;
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frac = <0x1400>;
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};
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
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pll3: st,pll@2 {
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compatible = "st,stm32mp1-pll";
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reg = <2>;
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cfg = <1 33 1 16 36 PQR(1,1,1)>;
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frac = <0x1a04>;
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};
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/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
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pll4: st,pll@3 {
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compatible = "st,stm32mp1-pll";
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reg = <3>;
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cfg = <3 98 5 7 7 PQR(1,1,1)>;
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};
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};
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&rng1 {
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status = "okay";
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};
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&rtc {
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status = "okay";
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};
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&sdmmc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>;
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non-removable;
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no-sd;
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no-sdio;
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st,neg-edge;
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bus-width = <8>;
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vmmc-supply = <&v3v3>;
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vqmmc-supply = <&vdd>;
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mmc-ddr-3_3v;
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status = "okay";
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};
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40
fdts/stm32mp157c-odyssey.dts
Normal file
40
fdts/stm32mp157c-odyssey.dts
Normal file
@ -0,0 +1,40 @@
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/*
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* Copyright (C) 2019, STMicroelectronics. All Rights Reserved.
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* Copyright (C) 2021, Grzegorz Szymaszek.
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*
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* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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*/
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/dts-v1/;
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#include "stm32mp157c-odyssey-som.dtsi"
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/ {
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model = "Seeed Studio Odyssey-STM32MP157C Board";
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compatible = "seeed,stm32mp157c-odyssey",
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"seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
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aliases {
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serial0 = &uart4;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&sdmmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc1_b4_pins_a>;
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disable-wp;
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st,neg-edge;
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bus-width = <4>;
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vmmc-supply = <&v3v3>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_pins_a>;
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||||
status = "okay";
|
||||
};
|
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Block a user