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feat(plat/st): use FIP to load images

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BL2 still uses the STM32 header binary format to be loaded from ROM code.
BL32 and BL33 and their respective device tree files are now put together
in a FIP file.
One DTB is created for each BL. To reduce their sizes, 2 new dtsi file are
in charge of removing useless nodes for a given BL. This is done because
BL2 and BL32 share the same device tree files base.

The previous way of booting is still available, the compilation flag
STM32MP_USE_STM32IMAGE has to be set to 1 in the make command. Some files
are duplicated and their names modified with _stm32_ to avoid too much
switches in the code.

Change-Id: I1ffada0af58486d4cf6044511b51e56b52269817
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
This commit is contained in:
Yann Gautier 2021-05-19 18:48:16 +02:00
parent 84090d2ca4
commit 1d204ee4ab
18 changed files with 1264 additions and 381 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
fdts/stm32mp15-bl2.dtsi Normal file
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@ -0,0 +1,30 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2020-2021 - All Rights Reserved
*/
/ {
cpus {
/delete-node/ cpu@1;
};
/delete-node/ psci;
soc {
/delete-node/ timer@40006000;
/delete-node/ timer@44006000;
/delete-node/ pwr_mcu@50001014;
/delete-node/ cryp@54001000;
/delete-node/ rng@54003000;
/delete-node/ spi@5c001000;
/delete-node/ rtc@5c004000;
/delete-node/ etzpc@5c007000;
/delete-node/ stgen@5c008000;
/delete-node/ i2c@5c009000;
/delete-node/ tamp@5c00a000;
pin-controller@50002000 {
/delete-node/ rtc-out2-rmp-pins-0;
};
};
};

44
fdts/stm32mp15-bl32.dtsi Normal file
View File

@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2020-2021 - All Rights Reserved
*/
/ {
aliases {
/delete-property/ mmc0;
/delete-property/ mmc1;
};
cpus {
/delete-node/ cpu@1;
};
/delete-node/ psci;
soc {
/delete-node/ usb-otg@49000000;
/delete-node/ hash@54002000;
/delete-node/ memory-controller@58002000;
/delete-node/ spi@58003000;
/delete-node/ sdmmc@58005000;
/delete-node/ sdmmc@58007000;
/delete-node/ usbphyc@5a006000;
/delete-node/ spi@5c001000;
/delete-node/ stgen@5c008000;
/delete-node/ i2c@5c009000;
pin-controller@50002000 {
/delete-node/ fmc-0;
/delete-node/ qspi-clk-0;
/delete-node/ qspi-bk1-0;
/delete-node/ qspi-bk2-0;
/delete-node/ sdmmc1-b4-0;
/delete-node/ sdmmc1-dir-0;
/delete-node/ sdmmc2-b4-0;
/delete-node/ sdmmc2-b4-1;
/delete-node/ sdmmc2-d47-0;
/delete-node/ usbotg_hs-0;
/delete-node/ usbotg-fs-dp-dm-0;
};
};
};

435
plat/st/common/bl2_io_storage.c
View File

@ -7,13 +7,11 @@
#include <assert.h>
#include <string.h>
#include <platform_def.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/io/io_block.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_dummy.h>
#include <drivers/io/io_fip.h>
#include <drivers/io/io_mtd.h>
#include <drivers/io/io_storage.h>
#include <drivers/mmc.h>
@ -22,29 +20,27 @@
#include <drivers/spi_nand.h>
#include <drivers/spi_nor.h>
#include <drivers/st/io_mmc.h>
#include <drivers/st/io_stm32image.h>
#include <drivers/st/stm32_fmc2_nand.h>
#include <drivers/st/stm32_qspi.h>
#include <drivers/st/stm32_sdmmc2.h>
#include <lib/mmio.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
#include <tools_share/firmware_image_package.h>
#include <platform_def.h>
/* IO devices */
#ifndef AARCH32_SP_OPTEE
static const io_dev_connector_t *dummy_dev_con;
static uintptr_t dummy_dev_handle;
static uintptr_t dummy_dev_spec;
#endif
uintptr_t fip_dev_handle;
uintptr_t storage_dev_handle;
static uintptr_t image_dev_handle;
static uintptr_t storage_dev_handle;
static const io_dev_connector_t *fip_dev_con;
#if STM32MP_SDMMC || STM32MP_EMMC
static struct mmc_device_info mmc_info;
static io_block_spec_t gpt_block_spec = {
.offset = 0,
.length = 34 * MMC_BLOCK_SIZE, /* Size of GPT table */
.offset = 0U,
.length = 34U * MMC_BLOCK_SIZE, /* Size of GPT table */
};
static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE);
@ -62,30 +58,6 @@ static const io_block_dev_spec_t mmc_block_dev_spec = {
.block_size = MMC_BLOCK_SIZE,
};
#if STM32MP_EMMC_BOOT
static io_block_spec_t emmc_boot_ssbl_block_spec = {
.offset = PLAT_EMMC_BOOT_SSBL_OFFSET,
.length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */
};
static const io_block_dev_spec_t mmc_block_dev_boot_part_spec = {
/* It's used as temp buffer in block driver */
.buffer = {
.offset = (size_t)&block_buffer,
.length = MMC_BLOCK_SIZE,
},
.ops = {
.read = mmc_boot_part_read_blocks,
.write = NULL,
},
.block_size = MMC_BLOCK_SIZE,
};
#endif
static struct io_mmc_dev_spec mmc_device_spec = {
.use_boot_part = false,
};
static const io_dev_connector_t *mmc_dev_con;
#endif /* STM32MP_SDMMC || STM32MP_EMMC */
@ -103,6 +75,7 @@ static io_mtd_dev_spec_t nand_dev_spec = {
.ops = {
.init = nand_raw_init,
.read = nand_read,
.seek = nand_seek_bb
},
};
@ -114,6 +87,7 @@ static io_mtd_dev_spec_t spi_nand_dev_spec = {
.ops = {
.init = spi_nand_init,
.read = nand_read,
.seek = nand_seek_bb
},
};
#endif
@ -122,76 +96,42 @@ static io_mtd_dev_spec_t spi_nand_dev_spec = {
static const io_dev_connector_t *spi_dev_con;
#endif
static const io_uuid_spec_t bl33_partition_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33
};
static const io_uuid_spec_t tos_fw_config_uuid_spec = {
.uuid = UUID_TOS_FW_CONFIG,
};
static const io_uuid_spec_t hw_config_uuid_spec = {
.uuid = UUID_HW_CONFIG,
};
#ifdef AARCH32_SP_OPTEE
static const struct stm32image_part_info optee_header_partition_spec = {
.name = OPTEE_HEADER_IMAGE_NAME,
.binary_type = OPTEE_HEADER_BINARY_TYPE,
static const io_uuid_spec_t optee_header_partition_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32
};
static const struct stm32image_part_info optee_core_partition_spec = {
.name = OPTEE_CORE_IMAGE_NAME,
.binary_type = OPTEE_CORE_BINARY_TYPE,
static const io_uuid_spec_t optee_core_partition_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1
};
static const struct stm32image_part_info optee_paged_partition_spec = {
.name = OPTEE_PAGED_IMAGE_NAME,
.binary_type = OPTEE_PAGED_BINARY_TYPE,
static const io_uuid_spec_t optee_paged_partition_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2
};
#else
static const io_block_spec_t bl32_block_spec = {
.offset = BL32_BASE,
.length = STM32MP_BL32_SIZE
static const io_uuid_spec_t bl32_partition_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32
};
#endif
static const struct stm32image_part_info bl33_partition_spec = {
.name = BL33_IMAGE_NAME,
.binary_type = BL33_BINARY_TYPE,
static io_block_spec_t image_block_spec = {
.offset = 0U,
.length = 0U,
};
enum {
IMG_IDX_BL33,
#ifdef AARCH32_SP_OPTEE
IMG_IDX_OPTEE_HEADER,
IMG_IDX_OPTEE_CORE,
IMG_IDX_OPTEE_PAGED,
#endif
IMG_IDX_NUM
};
static struct stm32image_device_info stm32image_dev_info_spec __unused = {
.lba_size = MMC_BLOCK_SIZE,
.part_info[IMG_IDX_BL33] = {
.name = BL33_IMAGE_NAME,
.binary_type = BL33_BINARY_TYPE,
},
#ifdef AARCH32_SP_OPTEE
.part_info[IMG_IDX_OPTEE_HEADER] = {
.name = OPTEE_HEADER_IMAGE_NAME,
.binary_type = OPTEE_HEADER_BINARY_TYPE,
},
.part_info[IMG_IDX_OPTEE_CORE] = {
.name = OPTEE_CORE_IMAGE_NAME,
.binary_type = OPTEE_CORE_BINARY_TYPE,
},
.part_info[IMG_IDX_OPTEE_PAGED] = {
.name = OPTEE_PAGED_IMAGE_NAME,
.binary_type = OPTEE_PAGED_BINARY_TYPE,
},
#endif
};
static io_block_spec_t stm32image_block_spec = {
.offset = 0,
.length = 0,
};
static const io_dev_connector_t *stm32image_dev_con __unused;
#ifndef AARCH32_SP_OPTEE
static int open_dummy(const uintptr_t spec);
#endif
static int open_image(const uintptr_t spec);
static int open_fip(const uintptr_t spec);
static int open_storage(const uintptr_t spec);
struct plat_io_policy {
@ -201,33 +141,48 @@ struct plat_io_policy {
};
static const struct plat_io_policy policies[] = {
[FIP_IMAGE_ID] = {
.dev_handle = &storage_dev_handle,
.image_spec = (uintptr_t)&image_block_spec,
.check = open_storage
},
#ifdef AARCH32_SP_OPTEE
[BL32_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.dev_handle = &fip_dev_handle,
.image_spec = (uintptr_t)&optee_header_partition_spec,
.check = open_image
.check = open_fip
},
[BL32_EXTRA1_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.dev_handle = &fip_dev_handle,
.image_spec = (uintptr_t)&optee_core_partition_spec,
.check = open_image
.check = open_fip
},
[BL32_EXTRA2_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.dev_handle = &fip_dev_handle,
.image_spec = (uintptr_t)&optee_paged_partition_spec,
.check = open_image
.check = open_fip
},
#else
[BL32_IMAGE_ID] = {
.dev_handle = &dummy_dev_handle,
.image_spec = (uintptr_t)&bl32_block_spec,
.check = open_dummy
.dev_handle = &fip_dev_handle,
.image_spec = (uintptr_t)&bl32_partition_spec,
.check = open_fip
},
#endif
[BL33_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.dev_handle = &fip_dev_handle,
.image_spec = (uintptr_t)&bl33_partition_spec,
.check = open_image
.check = open_fip
},
[TOS_FW_CONFIG_ID] = {
.dev_handle = &fip_dev_handle,
.image_spec = (uintptr_t)&tos_fw_config_uuid_spec,
.check = open_fip
},
[HW_CONFIG_ID] = {
.dev_handle = &fip_dev_handle,
.image_spec = (uintptr_t)&hw_config_uuid_spec,
.check = open_fip
},
#if STM32MP_SDMMC || STM32MP_EMMC
[GPT_IMAGE_ID] = {
@ -236,23 +191,11 @@ static const struct plat_io_policy policies[] = {
.check = open_storage
},
#endif
[STM32_IMAGE_ID] = {
.dev_handle = &storage_dev_handle,
.image_spec = (uintptr_t)&stm32image_block_spec,
.check = open_storage
}
};
#ifndef AARCH32_SP_OPTEE
static int open_dummy(const uintptr_t spec)
static int open_fip(const uintptr_t spec)
{
return io_dev_init(dummy_dev_handle, 0);
}
#endif
static int open_image(const uintptr_t spec)
{
return io_dev_init(image_dev_handle, 0);
return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
}
static int open_storage(const uintptr_t spec)
@ -260,38 +203,6 @@ static int open_storage(const uintptr_t spec)
return io_dev_init(storage_dev_handle, 0);
}
#if STM32MP_EMMC_BOOT
static uint32_t get_boot_part_ssbl_header(void)
{
uint32_t magic = 0;
int io_result;
size_t bytes_read;
io_result = register_io_dev_block(&mmc_dev_con);
if (io_result != 0) {
panic();
}
io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_boot_part_spec,
&storage_dev_handle);
assert(io_result == 0);
io_result = io_open(storage_dev_handle, (uintptr_t) &emmc_boot_ssbl_block_spec,
&image_dev_handle);
assert(io_result == 0);
io_result = io_read(image_dev_handle, (uintptr_t) &magic, sizeof(magic),
&bytes_read);
assert(io_result == 0);
assert(bytes_read == sizeof(magic));
io_result = io_dev_close(storage_dev_handle);
assert(io_result == 0);
return magic;
}
#endif
static void print_boot_device(boot_api_context_t *boot_context)
{
switch (boot_context->boot_interface_selected) {
@ -311,7 +222,8 @@ static void print_boot_device(boot_api_context_t *boot_context)
INFO("Using SPI NAND\n");
break;
default:
ERROR("Boot interface not found\n");
ERROR("Boot interface %u not found\n",
boot_context->boot_interface_selected);
panic();
break;
}
@ -321,29 +233,12 @@ static void print_boot_device(boot_api_context_t *boot_context)
}
}
static void stm32image_io_setup(void)
{
int io_result __unused;
io_result = register_io_dev_stm32image(&stm32image_dev_con);
assert(io_result == 0);
io_result = io_dev_open(stm32image_dev_con,
(uintptr_t)&stm32image_dev_info_spec,
&image_dev_handle);
assert(io_result == 0);
}
#if STM32MP_SDMMC || STM32MP_EMMC
static void boot_mmc(enum mmc_device_type mmc_dev_type,
uint16_t boot_interface_instance)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
struct stm32_sdmmc2_params params;
const partition_entry_t *entry __unused;
uint32_t magic __unused;
zeromem(&params, sizeof(struct stm32_sdmmc2_params));
@ -375,26 +270,6 @@ static void boot_mmc(enum mmc_device_type mmc_dev_type,
panic();
}
stm32image_dev_info_spec.device_size =
stm32_sdmmc2_mmc_get_device_size();
#if STM32MP_EMMC_BOOT
magic = get_boot_part_ssbl_header();
if (magic == BOOT_API_IMAGE_HEADER_MAGIC_NB) {
VERBOSE("%s, header found, jump to emmc load\n", __func__);
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = PLAT_EMMC_BOOT_SSBL_OFFSET;
part->bkp_offset = 0U;
mmc_device_spec.use_boot_part = true;
goto emmc_boot;
} else {
WARN("%s: Can't find STM32 header on a boot partition\n", __func__);
}
#endif
/* Open MMC as a block device to read GPT table */
io_result = register_io_dev_block(&mmc_dev_con);
if (io_result != 0) {
@ -404,37 +279,6 @@ static void boot_mmc(enum mmc_device_type mmc_dev_type,
io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
partition_init(GPT_IMAGE_ID);
io_result = io_dev_close(storage_dev_handle);
assert(io_result == 0);
for (idx = 0U; idx < IMG_IDX_NUM; idx++) {
part = &stm32image_dev_info_spec.part_info[idx];
entry = get_partition_entry(part->name);
if (entry == NULL) {
ERROR("Partition %s not found\n", part->name);
panic();
}
part->part_offset = entry->start;
part->bkp_offset = 0U;
}
#if STM32MP_EMMC_BOOT
emmc_boot:
#endif
/*
* Re-open MMC with io_mmc, for better perfs compared to
* io_block.
*/
io_result = register_io_dev_mmc(&mmc_dev_con);
assert(io_result == 0);
io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_device_spec,
&storage_dev_handle);
assert(io_result == 0);
}
#endif /* STM32MP_SDMMC || STM32MP_EMMC */
@ -442,8 +286,6 @@ emmc_boot:
static void boot_spi_nor(boot_api_context_t *boot_context)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
io_result = stm32_qspi_init();
assert(io_result == 0);
@ -456,30 +298,6 @@ static void boot_spi_nor(boot_api_context_t *boot_context)
(uintptr_t)&spi_nor_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
stm32image_dev_info_spec.device_size = spi_nor_dev_spec.device_size;
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_BL33_OFFSET;
part->bkp_offset = 0U;
#ifdef AARCH32_SP_OPTEE
idx = IMG_IDX_OPTEE_HEADER;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_TEEH_OFFSET;
part->bkp_offset = 0U;
idx = IMG_IDX_OPTEE_PAGED;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_TEED_OFFSET;
part->bkp_offset = 0U;
idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_TEEX_OFFSET;
part->bkp_offset = 0U;
#endif
}
#endif /* STM32MP_SPI_NOR */
@ -487,8 +305,6 @@ static void boot_spi_nor(boot_api_context_t *boot_context)
static void boot_fmc2_nand(boot_api_context_t *boot_context)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
io_result = stm32_fmc2_init();
assert(io_result == 0);
@ -501,30 +317,6 @@ static void boot_fmc2_nand(boot_api_context_t *boot_context)
io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
stm32image_dev_info_spec.device_size = nand_dev_spec.device_size;
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_BL33_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
#ifdef AARCH32_SP_OPTEE
idx = IMG_IDX_OPTEE_HEADER;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEH_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_PAGED;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEED_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEX_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
#endif
}
#endif /* STM32MP_RAW_NAND */
@ -532,8 +324,6 @@ static void boot_fmc2_nand(boot_api_context_t *boot_context)
static void boot_spi_nand(boot_api_context_t *boot_context)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
io_result = stm32_qspi_init();
assert(io_result == 0);
@ -546,31 +336,6 @@ static void boot_spi_nand(boot_api_context_t *boot_context)
(uintptr_t)&spi_nand_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
stm32image_dev_info_spec.device_size =
spi_nand_dev_spec.device_size;
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_BL33_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
#ifdef AARCH32_SP_OPTEE
idx = IMG_IDX_OPTEE_HEADER;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEH_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_PAGED;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEED_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEX_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
#endif
}
#endif /* STM32MP_SPI_NAND */
@ -584,53 +349,45 @@ void stm32mp_io_setup(void)
if ((boot_context->boot_partition_used_toboot == 1U) ||
(boot_context->boot_partition_used_toboot == 2U)) {
INFO("Boot used partition fsbl%d\n",
INFO("Boot used partition fsbl%u\n",
boot_context->boot_partition_used_toboot);
}
#ifndef AARCH32_SP_OPTEE
io_result = register_io_dev_dummy(&dummy_dev_con);
io_result = register_io_dev_fip(&fip_dev_con);
assert(io_result == 0);
io_result = io_dev_open(dummy_dev_con, dummy_dev_spec,
&dummy_dev_handle);
assert(io_result == 0);
#endif
io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
&fip_dev_handle);
switch (boot_context->boot_interface_selected) {
#if STM32MP_SDMMC
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
dmbsy();
boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance);
stm32image_io_setup();
break;
#endif
#if STM32MP_EMMC
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
dmbsy();
boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance);
stm32image_io_setup();
break;
#endif
#if STM32MP_SPI_NOR
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
dmbsy();
boot_spi_nor(boot_context);
stm32image_io_setup();
break;
#endif
#if STM32MP_RAW_NAND
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
dmbsy();
boot_fmc2_nand(boot_context);
stm32image_io_setup();
break;
#endif
#if STM32MP_SPI_NAND
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
dmbsy();
boot_spi_nand(boot_context);
stm32image_io_setup();
break;
#endif
@ -642,6 +399,60 @@ void stm32mp_io_setup(void)
}
}
int bl2_plat_handle_pre_image_load(unsigned int image_id)
{
static bool gpt_init_done __unused;
uint16_t boot_itf = stm32mp_get_boot_itf_selected();
switch (boot_itf) {
#if STM32MP_SDMMC || STM32MP_EMMC
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
if (!gpt_init_done) {
const partition_entry_t *entry;
partition_init(GPT_IMAGE_ID);
entry = get_partition_entry(FIP_IMAGE_NAME);
if (entry == NULL) {
ERROR("Could NOT find the %s partition!\n",
FIP_IMAGE_NAME);
return -ENOENT;
}
image_block_spec.offset = entry->start;
image_block_spec.length = entry->length;
gpt_init_done = true;
}
break;
#endif
#if STM32MP_RAW_NAND || STM32MP_SPI_NAND
#if STM32MP_RAW_NAND
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
#endif
#if STM32MP_SPI_NAND
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
#endif
image_block_spec.offset = STM32MP_NAND_FIP_OFFSET;
break;
#endif
#if STM32MP_SPI_NOR
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
image_block_spec.offset = STM32MP_NOR_FIP_OFFSET;
break;
#endif
default:
ERROR("FIP Not found\n");
panic();
}
return 0;
}
/*
* Return an IO device handle and specification which can be used to access
* an image. Use this to enforce platform load policy.

665
plat/st/common/bl2_stm32_io_storage.c Normal file
View File

@ -0,0 +1,665 @@
/*
* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <string.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/io/io_block.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_dummy.h>
#include <drivers/io/io_mtd.h>
#include <drivers/io/io_storage.h>
#include <drivers/mmc.h>
#include <drivers/partition/partition.h>
#include <drivers/raw_nand.h>
#include <drivers/spi_nand.h>
#include <drivers/spi_nor.h>
#include <drivers/st/io_mmc.h>
#include <drivers/st/io_stm32image.h>
#include <drivers/st/stm32_fmc2_nand.h>
#include <drivers/st/stm32_qspi.h>
#include <drivers/st/stm32_sdmmc2.h>
#include <lib/mmio.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
#include <platform_def.h>
/* IO devices */
#ifndef AARCH32_SP_OPTEE
static const io_dev_connector_t *dummy_dev_con;
static uintptr_t dummy_dev_handle;
static uintptr_t dummy_dev_spec;
#endif
static uintptr_t image_dev_handle;
static uintptr_t storage_dev_handle;
#if STM32MP_SDMMC || STM32MP_EMMC
static struct mmc_device_info mmc_info;
static io_block_spec_t gpt_block_spec = {
.offset = 0U,
.length = 34U * MMC_BLOCK_SIZE, /* Size of GPT table */
};
static uint32_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE);
static const io_block_dev_spec_t mmc_block_dev_spec = {
/* It's used as temp buffer in block driver */
.buffer = {
.offset = (size_t)&block_buffer,
.length = MMC_BLOCK_SIZE,
},
.ops = {
.read = mmc_read_blocks,
.write = NULL,
},
.block_size = MMC_BLOCK_SIZE,
};
#if STM32MP_EMMC_BOOT
static io_block_spec_t emmc_boot_ssbl_block_spec = {
.offset = PLAT_EMMC_BOOT_SSBL_OFFSET,
.length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */
};
static const io_block_dev_spec_t mmc_block_dev_boot_part_spec = {
/* It's used as temp buffer in block driver */
.buffer = {
.offset = (size_t)&block_buffer,
.length = MMC_BLOCK_SIZE,
},
.ops = {
.read = mmc_boot_part_read_blocks,
.write = NULL,
},
.block_size = MMC_BLOCK_SIZE,
};
#endif
static struct io_mmc_dev_spec mmc_device_spec = {
.use_boot_part = false,
};
static const io_dev_connector_t *mmc_dev_con;
#endif /* STM32MP_SDMMC || STM32MP_EMMC */
#if STM32MP_SPI_NOR
static io_mtd_dev_spec_t spi_nor_dev_spec = {
.ops = {
.init = spi_nor_init,
.read = spi_nor_read,
},
};
#endif
#if STM32MP_RAW_NAND
static io_mtd_dev_spec_t nand_dev_spec = {
.ops = {
.init = nand_raw_init,
.read = nand_read,
},
};
static const io_dev_connector_t *nand_dev_con;
#endif
#if STM32MP_SPI_NAND
static io_mtd_dev_spec_t spi_nand_dev_spec = {
.ops = {
.init = spi_nand_init,
.read = nand_read,
},
};
#endif
#if STM32MP_SPI_NAND || STM32MP_SPI_NOR
static const io_dev_connector_t *spi_dev_con;
#endif
#ifdef AARCH32_SP_OPTEE
static const struct stm32image_part_info optee_header_partition_spec = {
.name = OPTEE_HEADER_IMAGE_NAME,
.binary_type = OPTEE_HEADER_BINARY_TYPE,
};
static const struct stm32image_part_info optee_core_partition_spec = {
.name = OPTEE_CORE_IMAGE_NAME,
.binary_type = OPTEE_CORE_BINARY_TYPE,
};
static const struct stm32image_part_info optee_paged_partition_spec = {
.name = OPTEE_PAGED_IMAGE_NAME,
.binary_type = OPTEE_PAGED_BINARY_TYPE,
};
#else
static const io_block_spec_t bl32_block_spec = {
.offset = BL32_BASE,
.length = STM32MP_BL32_SIZE
};
#endif
static const struct stm32image_part_info bl33_partition_spec = {
.name = BL33_IMAGE_NAME,
.binary_type = BL33_BINARY_TYPE,
};
enum {
IMG_IDX_BL33,
#ifdef AARCH32_SP_OPTEE
IMG_IDX_OPTEE_HEADER,
IMG_IDX_OPTEE_CORE,
IMG_IDX_OPTEE_PAGED,
#endif
IMG_IDX_NUM
};
static struct stm32image_device_info stm32image_dev_info_spec __unused = {
.lba_size = MMC_BLOCK_SIZE,
.part_info[IMG_IDX_BL33] = {
.name = BL33_IMAGE_NAME,
.binary_type = BL33_BINARY_TYPE,
},
#ifdef AARCH32_SP_OPTEE
.part_info[IMG_IDX_OPTEE_HEADER] = {
.name = OPTEE_HEADER_IMAGE_NAME,
.binary_type = OPTEE_HEADER_BINARY_TYPE,
},
.part_info[IMG_IDX_OPTEE_CORE] = {
.name = OPTEE_CORE_IMAGE_NAME,
.binary_type = OPTEE_CORE_BINARY_TYPE,
},
.part_info[IMG_IDX_OPTEE_PAGED] = {
.name = OPTEE_PAGED_IMAGE_NAME,
.binary_type = OPTEE_PAGED_BINARY_TYPE,
},
#endif
};
static io_block_spec_t stm32image_block_spec = {
.offset = 0U,
.length = 0U,
};
static const io_dev_connector_t *stm32image_dev_con __unused;
#ifndef AARCH32_SP_OPTEE
static int open_dummy(const uintptr_t spec);
#endif
static int open_image(const uintptr_t spec);
static int open_storage(const uintptr_t spec);
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int (*check)(const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
#ifdef AARCH32_SP_OPTEE
[BL32_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.image_spec = (uintptr_t)&optee_header_partition_spec,
.check = open_image
},
[BL32_EXTRA1_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.image_spec = (uintptr_t)&optee_core_partition_spec,
.check = open_image
},
[BL32_EXTRA2_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.image_spec = (uintptr_t)&optee_paged_partition_spec,
.check = open_image
},
#else
[BL32_IMAGE_ID] = {
.dev_handle = &dummy_dev_handle,
.image_spec = (uintptr_t)&bl32_block_spec,
.check = open_dummy
},
#endif
[BL33_IMAGE_ID] = {
.dev_handle = &image_dev_handle,
.image_spec = (uintptr_t)&bl33_partition_spec,
.check = open_image
},
#if STM32MP_SDMMC || STM32MP_EMMC
[GPT_IMAGE_ID] = {
.dev_handle = &storage_dev_handle,
.image_spec = (uintptr_t)&gpt_block_spec,
.check = open_storage
},
#endif
[STM32_IMAGE_ID] = {
.dev_handle = &storage_dev_handle,
.image_spec = (uintptr_t)&stm32image_block_spec,
.check = open_storage
}
};
#ifndef AARCH32_SP_OPTEE
static int open_dummy(const uintptr_t spec)
{
return io_dev_init(dummy_dev_handle, 0);
}
#endif
static int open_image(const uintptr_t spec)
{
return io_dev_init(image_dev_handle, 0);
}
static int open_storage(const uintptr_t spec)
{
return io_dev_init(storage_dev_handle, 0);
}
#if STM32MP_EMMC_BOOT
static uint32_t get_boot_part_ssbl_header(void)
{
uint32_t magic = 0U;
int io_result;
size_t bytes_read;
io_result = register_io_dev_block(&mmc_dev_con);
if (io_result != 0) {
panic();
}
io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_boot_part_spec,
&storage_dev_handle);
assert(io_result == 0);
io_result = io_open(storage_dev_handle, (uintptr_t)&emmc_boot_ssbl_block_spec,
&image_dev_handle);
assert(io_result == 0);
io_result = io_read(image_dev_handle, (uintptr_t)&magic, sizeof(magic),
&bytes_read);
assert(io_result == 0);
assert(bytes_read == sizeof(magic));
io_result = io_dev_close(storage_dev_handle);
assert(io_result == 0);
return magic;
}
#endif
static void print_boot_device(boot_api_context_t *boot_context)
{
switch (boot_context->boot_interface_selected) {
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
INFO("Using SDMMC\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
INFO("Using EMMC\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
INFO("Using QSPI NOR\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
INFO("Using FMC NAND\n");
break;
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
INFO("Using SPI NAND\n");
break;
default:
ERROR("Boot interface not found\n");
panic();
break;
}
if (boot_context->boot_interface_instance != 0U) {
INFO(" Instance %d\n", boot_context->boot_interface_instance);
}
}
static void stm32image_io_setup(void)
{
int io_result __unused;
io_result = register_io_dev_stm32image(&stm32image_dev_con);
assert(io_result == 0);
io_result = io_dev_open(stm32image_dev_con,
(uintptr_t)&stm32image_dev_info_spec,
&image_dev_handle);
assert(io_result == 0);
}
#if STM32MP_SDMMC || STM32MP_EMMC
static void boot_mmc(enum mmc_device_type mmc_dev_type,
uint16_t boot_interface_instance)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
struct stm32_sdmmc2_params params;
const partition_entry_t *entry __unused;
uint32_t magic __unused;
zeromem(&params, sizeof(struct stm32_sdmmc2_params));
mmc_info.mmc_dev_type = mmc_dev_type;
switch (boot_interface_instance) {
case 1:
params.reg_base = STM32MP_SDMMC1_BASE;
break;
case 2:
params.reg_base = STM32MP_SDMMC2_BASE;
break;
case 3:
params.reg_base = STM32MP_SDMMC3_BASE;
break;
default:
WARN("SDMMC instance not found, using default\n");
if (mmc_dev_type == MMC_IS_SD) {
params.reg_base = STM32MP_SDMMC1_BASE;
} else {
params.reg_base = STM32MP_SDMMC2_BASE;
}
break;
}
params.device_info = &mmc_info;
if (stm32_sdmmc2_mmc_init(&params) != 0) {
ERROR("SDMMC%u init failed\n", boot_interface_instance);
panic();
}
stm32image_dev_info_spec.device_size =
stm32_sdmmc2_mmc_get_device_size();
#if STM32MP_EMMC_BOOT
magic = get_boot_part_ssbl_header();
if (magic == BOOT_API_IMAGE_HEADER_MAGIC_NB) {
VERBOSE("%s, header found, jump to emmc load\n", __func__);
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = PLAT_EMMC_BOOT_SSBL_OFFSET;
part->bkp_offset = 0U;
mmc_device_spec.use_boot_part = true;
goto emmc_boot;
} else {
WARN("%s: Can't find STM32 header on a boot partition\n", __func__);
}
#endif
/* Open MMC as a block device to read GPT table */
io_result = register_io_dev_block(&mmc_dev_con);
if (io_result != 0) {
panic();
}
io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
partition_init(GPT_IMAGE_ID);
io_result = io_dev_close(storage_dev_handle);
assert(io_result == 0);
for (idx = 0U; idx < IMG_IDX_NUM; idx++) {
part = &stm32image_dev_info_spec.part_info[idx];
entry = get_partition_entry(part->name);
if (entry == NULL) {
ERROR("Partition %s not found\n", part->name);
panic();
}
part->part_offset = entry->start;
part->bkp_offset = 0U;
}
#if STM32MP_EMMC_BOOT
emmc_boot:
#endif
/*
* Re-open MMC with io_mmc, for better perfs compared to
* io_block.
*/
io_result = register_io_dev_mmc(&mmc_dev_con);
assert(io_result == 0);
io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_device_spec,
&storage_dev_handle);
assert(io_result == 0);
}
#endif /* STM32MP_SDMMC || STM32MP_EMMC */
#if STM32MP_SPI_NOR
static void boot_spi_nor(boot_api_context_t *boot_context)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
io_result = stm32_qspi_init();
assert(io_result == 0);
io_result = register_io_dev_mtd(&spi_dev_con);
assert(io_result == 0);
/* Open connections to device */
io_result = io_dev_open(spi_dev_con,
(uintptr_t)&spi_nor_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
stm32image_dev_info_spec.device_size = spi_nor_dev_spec.device_size;
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_BL33_OFFSET;
part->bkp_offset = 0U;
#ifdef AARCH32_SP_OPTEE
idx = IMG_IDX_OPTEE_HEADER;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_TEEH_OFFSET;
part->bkp_offset = 0U;
idx = IMG_IDX_OPTEE_PAGED;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_TEED_OFFSET;
part->bkp_offset = 0U;
idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NOR_TEEX_OFFSET;
part->bkp_offset = 0U;
#endif
}
#endif /* STM32MP_SPI_NOR */
#if STM32MP_RAW_NAND
static void boot_fmc2_nand(boot_api_context_t *boot_context)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
io_result = stm32_fmc2_init();
assert(io_result == 0);
/* Register the IO device on this platform */
io_result = register_io_dev_mtd(&nand_dev_con);
assert(io_result == 0);
/* Open connections to device */
io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
stm32image_dev_info_spec.device_size = nand_dev_spec.device_size;
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_BL33_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
#ifdef AARCH32_SP_OPTEE
idx = IMG_IDX_OPTEE_HEADER;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEH_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_PAGED;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEED_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEX_OFFSET;
part->bkp_offset = nand_dev_spec.erase_size;
#endif
}
#endif /* STM32MP_RAW_NAND */
#if STM32MP_SPI_NAND
static void boot_spi_nand(boot_api_context_t *boot_context)
{
int io_result __unused;
uint8_t idx;
struct stm32image_part_info *part;
io_result = stm32_qspi_init();
assert(io_result == 0);
io_result = register_io_dev_mtd(&spi_dev_con);
assert(io_result == 0);
/* Open connections to device */
io_result = io_dev_open(spi_dev_con,
(uintptr_t)&spi_nand_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
stm32image_dev_info_spec.device_size =
spi_nand_dev_spec.device_size;
idx = IMG_IDX_BL33;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_BL33_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
#ifdef AARCH32_SP_OPTEE
idx = IMG_IDX_OPTEE_HEADER;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEH_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_PAGED;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEED_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
idx = IMG_IDX_OPTEE_CORE;
part = &stm32image_dev_info_spec.part_info[idx];
part->part_offset = STM32MP_NAND_TEEX_OFFSET;
part->bkp_offset = spi_nand_dev_spec.erase_size;
#endif
}
#endif /* STM32MP_SPI_NAND */
void stm32mp_io_setup(void)
{
int io_result __unused;
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
print_boot_device(boot_context);
if ((boot_context->boot_partition_used_toboot == 1U) ||
(boot_context->boot_partition_used_toboot == 2U)) {
INFO("Boot used partition fsbl%u\n",
boot_context->boot_partition_used_toboot);
}
#ifndef AARCH32_SP_OPTEE
io_result = register_io_dev_dummy(&dummy_dev_con);
assert(io_result == 0);
io_result = io_dev_open(dummy_dev_con, dummy_dev_spec,
&dummy_dev_handle);
assert(io_result == 0);
#endif
switch (boot_context->boot_interface_selected) {
#if STM32MP_SDMMC
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
dmbsy();
boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance);
stm32image_io_setup();
break;
#endif
#if STM32MP_EMMC
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
dmbsy();
boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance);
stm32image_io_setup();
break;
#endif
#if STM32MP_SPI_NOR
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_QSPI:
dmbsy();
boot_spi_nor(boot_context);
stm32image_io_setup();
break;
#endif
#if STM32MP_RAW_NAND
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC:
dmbsy();
boot_fmc2_nand(boot_context);
stm32image_io_setup();
break;
#endif
#if STM32MP_SPI_NAND
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_QSPI:
dmbsy();
boot_spi_nand(boot_context);
stm32image_io_setup();
break;
#endif
default:
ERROR("Boot interface %d not supported\n",
boot_context->boot_interface_selected);
panic();
break;
}
}
/*
* Return an IO device handle and specification which can be used to access
* an image. Use this to enforce platform load policy.
*/
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
int rc;
const struct plat_io_policy *policy;
assert(image_id < ARRAY_SIZE(policies));
policy = &policies[image_id];
rc = policy->check(policy->image_spec);
if (rc == 0) {
*image_spec = policy->image_spec;
*dev_handle = *(policy->dev_handle);
}
return rc;
}

2
plat/st/common/include/stm32mp_common.h
View File

@ -95,6 +95,7 @@ unsigned long stm32mp_clk_get_rate(unsigned long id);
/* Initialise the IO layer and register platform IO devices */
void stm32mp_io_setup(void);
#if STM32MP_USE_STM32IMAGE
/*
* Check that the STM32 header of a .stm32 binary image is valid
* @param header: pointer to the stm32 image header
@ -102,6 +103,7 @@ void stm32mp_io_setup(void);
* @return: 0 on success, negative value in case of error
*/
int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer);
#endif /* STM32MP_USE_STM32IMAGE */
/* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */
int stm32mp_map_ddr_non_cacheable(void);

2
plat/st/common/stm32mp_common.c
View File

@ -76,6 +76,7 @@ bool stm32mp_lock_available(void)
return (read_sctlr() & c_m_bits) == c_m_bits;
}
#if STM32MP_USE_STM32IMAGE
int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer)
{
uint32_t i;
@ -109,6 +110,7 @@ int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer)
return 0;
}
#endif /* STM32MP_USE_STM32IMAGE */
int stm32mp_map_ddr_non_cacheable(void)
{

18
plat/st/stm32mp1/bl2_plat_setup.c
View File

@ -151,11 +151,13 @@ void bl2_platform_setup(void)
panic();
}
#if STM32MP_USE_STM32IMAGE
#ifdef AARCH32_SP_OPTEE
INFO("BL2 runs OP-TEE setup\n");
#else
INFO("BL2 runs SP_MIN setup\n");
#endif
#endif /* STM32MP_USE_STM32IMAGE */
}
void bl2_el3_plat_arch_setup(void)
@ -173,6 +175,7 @@ void bl2_el3_plat_arch_setup(void)
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
#if STM32MP_USE_STM32IMAGE
#ifdef AARCH32_SP_OPTEE
mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
STM32MP_OPTEE_SIZE,
@ -183,6 +186,8 @@ void bl2_el3_plat_arch_setup(void)
BL32_LIMIT - BL32_BASE,
MT_RO_DATA | MT_SECURE);
#endif
#endif /* STM32MP_USE_STM32IMAGE */
/* Prevent corruption of preloaded Device Tree */
mmap_add_region(DTB_BASE, DTB_BASE,
DTB_LIMIT - DTB_BASE,
@ -324,7 +329,6 @@ skip_console_init:
stm32mp_io_setup();
}
#if defined(AARCH32_SP_OPTEE)
/*******************************************************************************
* This function can be used by the platforms to update/use image
* information for given `image_id`.
@ -334,8 +338,8 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
int err = 0;
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
bl_mem_params_node_t *bl32_mem_params;
bl_mem_params_node_t *pager_mem_params;
bl_mem_params_node_t *paged_mem_params;
bl_mem_params_node_t *pager_mem_params __unused;
bl_mem_params_node_t *paged_mem_params __unused;
assert(bl_mem_params != NULL);
@ -348,6 +352,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
assert((pager_mem_params != NULL) && (paged_mem_params != NULL));
#if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE)
/* Set OP-TEE extra image load areas at run-time */
pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE;
pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE;
@ -357,6 +362,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
STM32MP_DDR_S_SIZE -
STM32MP_DDR_SHMEM_SIZE;
paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE;
#endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */
err = parse_optee_header(&bl_mem_params->ep_info,
&pager_mem_params->image_info,
@ -370,6 +376,11 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base;
bl_mem_params->ep_info.args.arg1 = 0; /* Unused */
bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */
} else {
#if !STM32MP_USE_STM32IMAGE
bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base;
#endif /* !STM32MP_USE_STM32IMAGE */
bl_mem_params->ep_info.args.arg0 = 0;
}
break;
@ -391,4 +402,3 @@ void bl2_el3_plat_prepare_exit(void)
{
stm32mp1_security_setup();
}
#endif

8
plat/st/stm32mp1/include/platform_def.h
View File

@ -25,6 +25,7 @@
#define PLATFORM_STACK_SIZE 0xC00
#endif
#if STM32MP_USE_STM32IMAGE
#ifdef AARCH32_SP_OPTEE
#define OPTEE_HEADER_IMAGE_NAME "teeh"
#define OPTEE_CORE_IMAGE_NAME "teex"
@ -37,6 +38,9 @@
/* SSBL = second stage boot loader */
#define BL33_IMAGE_NAME "ssbl"
#define BL33_BINARY_TYPE U(0x0)
#else /* STM32MP_USE_STM32IMAGE */
#define FIP_IMAGE_NAME "fip"
#endif /* STM32MP_USE_STM32IMAGE */
#define STM32MP_PRIMARY_CPU U(0x0)
#define STM32MP_SECONDARY_CPU U(0x1)
@ -67,7 +71,7 @@
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
#ifndef AARCH32_SP_OPTEE
#if STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32)
#if ENABLE_PIE
#define BL32_BASE 0
#define BL32_LIMIT STM32MP_BL32_SIZE
@ -76,7 +80,7 @@
#define BL32_LIMIT (STM32MP_BL32_BASE + \
STM32MP_BL32_SIZE)
#endif
#endif
#endif /* STM32MP_USE_STM32IMAGE || defined(IMAGE_BL32) */
/*******************************************************************************
* BL33 specific defines.

36
plat/st/stm32mp1/plat_bl2_mem_params_desc.c
View File

@ -4,12 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
#include <common/bl_common.h>
#include <common/desc_image_load.h>
#include <plat/common/platform.h>
#include <platform_def.h>
/*******************************************************************************
* Following descriptor provides BL image/ep information that gets used
* by BL2 to load the images and also subset of this information is
@ -75,7 +75,37 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
.next_handoff_image_id = INVALID_IMAGE_ID,
},
#endif /* AARCH32_SP_OPTEE */
/* Fill HW_CONFIG related information if it exists */
{
.image_id = HW_CONFIG_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
VERSION_2, entry_point_info_t,
NON_SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t,
0U),
.image_info.image_base = STM32MP_HW_CONFIG_BASE,
.image_info.image_max_size =
PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_HW_CONFIG_BASE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
#if !defined(AARCH32_SP_OPTEE)
{
.image_id = TOS_FW_CONFIG_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
VERSION_2, entry_point_info_t,
SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t,
0U),
.image_info.image_base = STM32MP_BL32_DTB_BASE,
.image_info.image_max_size = STM32MP_BL32_DTB_SIZE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
#endif
/* Fill BL33 related information */
{
.image_id = BL33_IMAGE_ID,
@ -90,7 +120,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
DISABLE_ALL_EXCEPTIONS),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
VERSION_2, image_info_t, 0U),
.image_info.image_base = PLAT_STM32MP_NS_IMAGE_OFFSET,
.image_info.image_max_size = STM32MP_DDR_MAX_SIZE -

103
plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c Normal file
View File

@ -0,0 +1,103 @@
/*
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/bl_common.h>
#include <common/desc_image_load.h>
#include <plat/common/platform.h>
#include <platform_def.h>
/*******************************************************************************
* Following descriptor provides BL image/ep information that gets used
* by BL2 to load the images and also subset of this information is
* passed to next BL image. The image loading sequence is managed by
* populating the images in required loading order. The image execution
* sequence is managed by populating the `next_handoff_image_id` with
* the next executable image id.
******************************************************************************/
static bl_mem_params_node_t bl2_mem_params_descs[] = {
/* Fill BL32 related information */
{
.image_id = BL32_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
SECURE | EXECUTABLE | EP_FIRST_EXE),
/* Updated at runtime if OP-TEE is loaded */
.ep_info.pc = STM32MP_BL32_BASE,
.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
SPSR_E_LITTLE,
DISABLE_ALL_EXCEPTIONS),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
IMAGE_ATTRIB_PLAT_SETUP),
/* Updated at runtime if OP-TEE is loaded */
.image_info.image_base = STM32MP_BL32_BASE,
.image_info.image_max_size = STM32MP_BL32_SIZE,
.next_handoff_image_id = BL33_IMAGE_ID,
},
#if defined(AARCH32_SP_OPTEE)
/* Fill BL32 external 1 image related information */
{
.image_id = BL32_EXTRA1_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
IMAGE_ATTRIB_SKIP_LOADING),
.next_handoff_image_id = INVALID_IMAGE_ID,
},
/* Fill BL32 external 2 image related information */
{
.image_id = BL32_EXTRA2_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
IMAGE_ATTRIB_SKIP_LOADING),
.next_handoff_image_id = INVALID_IMAGE_ID,
},
#endif /* AARCH32_SP_OPTEE */
/* Fill BL33 related information */
{
.image_id = BL33_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
NON_SECURE | EXECUTABLE),
.ep_info.pc = PLAT_STM32MP_NS_IMAGE_OFFSET,
.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
SPSR_E_LITTLE,
DISABLE_ALL_EXCEPTIONS),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0U),
.image_info.image_base = PLAT_STM32MP_NS_IMAGE_OFFSET,
.image_info.image_max_size = STM32MP_DDR_MAX_SIZE -
(PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_DDR_BASE),
.next_handoff_image_id = INVALID_IMAGE_ID,
}
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)

10
plat/st/stm32mp1/plat_image_load.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -23,12 +23,14 @@ void plat_flush_next_bl_params(void)
******************************************************************************/
bl_load_info_t *plat_get_bl_image_load_info(void)
{
#if STM32MP_USE_STM32IMAGE
bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID);
uint32_t ddr_ns_size = stm32mp_get_ddr_ns_size();
/* Max size is non-secure DDR end address minus image_base */
bl33->image_info.image_max_size = STM32MP_DDR_BASE + ddr_ns_size -
bl33->image_info.image_base;
#endif /* STM32MP_USE_STM32IMAGE */
return get_bl_load_info_from_mem_params_desc();
}
@ -38,5 +40,9 @@ bl_load_info_t *plat_get_bl_image_load_info(void)
******************************************************************************/
bl_params_t *plat_get_next_bl_params(void)
{
return get_next_bl_params_from_mem_params_desc();
bl_params_t *bl_params = get_next_bl_params_from_mem_params_desc();
populate_next_bl_params_config(bl_params);
return bl_params;
}

89
plat/st/stm32mp1/platform.mk
View File

@ -9,7 +9,14 @@ ARM_WITH_NEON := yes
BL2_AT_EL3 := 1
USE_COHERENT_MEM := 0
# Allow TF-A to concatenate BL2 & BL32 binaries in a single file,
# share DTB file between BL2 and BL32
# If it is set to 0, then FIP is used
STM32MP_USE_STM32IMAGE ?= 0
ifneq ($(STM32MP_USE_STM32IMAGE),1)
ENABLE_PIE := 1
endif
STM32_TF_VERSION ?= 0
@ -29,8 +36,10 @@ STM32_TF_A_COPIES := 2
STM32_BL33_PARTS_NUM := 1
ifeq ($(AARCH32_SP),optee)
STM32_RUNTIME_PARTS_NUM := 3
else
else ifeq ($(STM32MP_USE_STM32IMAGE),1)
STM32_RUNTIME_PARTS_NUM := 0
else
STM32_RUNTIME_PARTS_NUM := 1
endif
PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + \
$(STM32_BL33_PARTS_NUM) + \
@ -46,7 +55,21 @@ STM32MP_EMMC_BOOT ?= 0
# Device tree
DTB_FILE_NAME ?= stm32mp157c-ev1.dtb
ifeq ($(STM32MP_USE_STM32IMAGE),1)
ifeq ($(AARCH32_SP),optee)
BL2_DTSI := stm32mp15-bl2.dtsi
FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
else
FDT_SOURCES := $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(DTB_FILE_NAME)))
endif
else
BL2_DTSI := stm32mp15-bl2.dtsi
FDT_SOURCES := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl2.dts,$(DTB_FILE_NAME)))
ifeq ($(AARCH32_SP),sp_min)
BL32_DTSI := stm32mp15-bl32.dtsi
FDT_SOURCES += $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dts,$(DTB_FILE_NAME)))
endif
endif
DTC_FLAGS += -Wno-unit_address_vs_reg
# Macros and rules to build TF binary
@ -66,6 +89,26 @@ STM32IMAGEPATH ?= tools/stm32image
STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT}
STM32IMAGE_SRC := ${STM32IMAGEPATH}/stm32image.c
ifneq (${STM32MP_USE_STM32IMAGE},1)
FIP_DEPS += dtbs
STM32MP_HW_CONFIG := ${BL33_CFG}
# Add the HW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_HW_CONFIG},--hw-config))
ifeq ($(AARCH32_SP),sp_min)
STM32MP_TOS_FW_CONFIG := $(addprefix ${BUILD_PLAT}/fdts/, $(patsubst %.dtb,%-bl32.dtb,$(DTB_FILE_NAME)))
$(eval $(call TOOL_ADD_PAYLOAD,${STM32MP_TOS_FW_CONFIG},--tos-fw-config))
else
# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
# in the FIP if the platform requires.
ifneq ($(BL32_EXTRA1),)
$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
endif
ifneq ($(BL32_EXTRA2),)
$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
endif
endif
endif
# Enable flags for C files
$(eval $(call assert_booleans,\
$(sort \
@ -76,6 +119,7 @@ $(eval $(call assert_booleans,\
STM32MP_SPI_NOR \
STM32MP_EMMC_BOOT \
PLAT_XLAT_TABLES_DYNAMIC \
STM32MP_USE_STM32IMAGE \
)))
$(eval $(call assert_numerics,\
@ -95,6 +139,7 @@ $(eval $(call add_defines,\
PLAT_XLAT_TABLES_DYNAMIC \
STM32_TF_A_COPIES \
PLAT_PARTITION_MAX_ENTRIES \
STM32MP_USE_STM32IMAGE \
)))
# Include paths and source files
@ -138,14 +183,22 @@ PLAT_BL_COMMON_SOURCES += drivers/arm/tzc/tzc400.c \
plat/st/stm32mp1/stm32mp1_security.c \
plat/st/stm32mp1/stm32mp1_syscfg.c
ifneq (${STM32MP_USE_STM32IMAGE},1)
BL2_SOURCES += drivers/io/io_fip.c \
plat/st/common/bl2_io_storage.c \
plat/st/stm32mp1/plat_bl2_mem_params_desc.c
else
BL2_SOURCES += drivers/io/io_dummy.c \
drivers/st/io/io_stm32image.c \
plat/st/common/bl2_stm32_io_storage.c \
plat/st/stm32mp1/plat_bl2_stm32_mem_params_desc.c
endif
BL2_SOURCES += drivers/io/io_block.c \
drivers/io/io_dummy.c \
drivers/io/io_mtd.c \
drivers/io/io_storage.c \
drivers/st/crypto/stm32_hash.c \
drivers/st/io/io_stm32image.c \
plat/st/common/stm32mp_auth.c \
plat/st/common/bl2_io_storage.c \
plat/st/stm32mp1/bl2_plat_setup.c
ifneq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC}),)
@ -187,12 +240,9 @@ BL2_SOURCES += drivers/st/ddr/stm32mp1_ddr.c \
drivers/st/ddr/stm32mp1_ram.c
BL2_SOURCES += common/desc_image_load.c \
plat/st/stm32mp1/plat_bl2_mem_params_desc.c \
plat/st/stm32mp1/plat_image_load.c
ifeq ($(AARCH32_SP),optee)
BL2_SOURCES += lib/optee/optee_utils.c
endif
# Compilation rules
.PHONY: check_dtc_version stm32image clean_stm32image check_boot_device
@ -230,12 +280,35 @@ check_dtc_version:
false; \
fi
ifeq ($(STM32MP_USE_STM32IMAGE)-$(AARCH32_SP),1-sp_min)
${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%.dtb plat/st/stm32mp1/stm32mp1.S bl2 ${BL32_DEP}
@echo " AS stm32mp1.S"
${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \
-DDTB_BIN_PATH=\"$<\" \
-c $(word 2,$^) -o $@
else
# Create DTB file for BL2
${BUILD_PLAT}/fdts/%-bl2.dts: fdts/%.dts fdts/${BL2_DTSI} | ${BUILD_PLAT} fdt_dirs
@echo '#include "$(patsubst fdts/%,%,$<)"' > $@
@echo '#include "${BL2_DTSI}"' >> $@
${BUILD_PLAT}/fdts/%-bl2.dtb: ${BUILD_PLAT}/fdts/%-bl2.dts
ifeq ($(AARCH32_SP),sp_min)
# Create DTB file for BL32
${BUILD_PLAT}/fdts/%-bl32.dts: fdts/%.dts fdts/${BL32_DTSI} | ${BUILD_PLAT} fdt_dirs
@echo '#include "$(patsubst fdts/%,%,$<)"' > $@
@echo '#include "${BL32_DTSI}"' >> $@
${BUILD_PLAT}/fdts/%-bl32.dtb: ${BUILD_PLAT}/fdts/%-bl32.dts
endif
${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%-bl2.dtb plat/st/stm32mp1/stm32mp1.S bl2
@echo " AS stm32mp1.S"
${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \
-DDTB_BIN_PATH=\"$<\" \
-c plat/st/stm32mp1/stm32mp1.S -o $@
endif
$(eval $(call MAKE_LD,${STM32_TF_LINKERFILE},plat/st/stm32mp1/stm32mp1.ld.S,2))

10
plat/st/stm32mp1/sp_min/sp_min_setup.c
View File

@ -140,6 +140,16 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
while (bl_params != NULL) {
if (bl_params->image_id == BL33_IMAGE_ID) {
bl33_image_ep_info = *bl_params->ep_info;
/*
* Check if hw_configuration is given to BL32 and
* share it to BL33.
*/
if (arg2 != 0U) {
bl33_image_ep_info.args.arg0 = 0U;
bl33_image_ep_info.args.arg1 = 0U;
bl33_image_ep_info.args.arg2 = arg2;
}
break;
}

4
plat/st/stm32mp1/stm32mp1.S
View File

@ -1,13 +1,15 @@
/*
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#if STM32MP_USE_STM32IMAGE
#ifdef BL32_BIN_PATH
.section .bl32_image
.incbin BL32_BIN_PATH
#endif
#endif /* STM32MP_USE_STM32IMAGE */
.section .bl2_image
.incbin BL2_BIN_PATH

10
plat/st/stm32mp1/stm32mp1.ld.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -43,7 +43,11 @@ SECTIONS
* The strongest and only alignment contraint is MMU 4K page.
* Indeed as images below will be removed, 4K pages will be re-used.
*/
#if STM32MP_USE_STM32IMAGE
. = ( STM32MP_DTB_BASE - STM32MP_BINARY_BASE );
#else
. = ( STM32MP_BL2_DTB_BASE - STM32MP_BINARY_BASE );
#endif /* STM32MP_USE_STM32IMAGE */
__DTB_IMAGE_START__ = .;
*(.dtb_image*)
__DTB_IMAGE_END__ = .;
@ -58,7 +62,7 @@ SECTIONS
*(.bl2_image*)
__BL2_IMAGE_END__ = .;
#ifndef AARCH32_SP_OPTEE
#if STM32MP_USE_STM32IMAGE && !defined(AARCH32_SP_OPTEE)
/*
* bl32 will be settled by bl2.
* The strongest and only alignment constraint is 8 words to simplify
@ -68,7 +72,7 @@ SECTIONS
__BL32_IMAGE_START__ = .;
*(.bl32_image*)
__BL32_IMAGE_END__ = .;
#endif
#endif /* STM32MP_USE_STM32IMAGE && !defined(AARCH32_SP_OPTEE) */
__DATA_END__ = .;
} >RAM

53
plat/st/stm32mp1/stm32mp1_def.h
View File

@ -28,6 +28,12 @@
#include <stm32mp1_shared_resources.h>
#endif
#if !STM32MP_USE_STM32IMAGE
#include "stm32mp1_fip_def.h"
#else /* STM32MP_USE_STM32IMAGE */
#include "stm32mp1_stm32image_def.h"
#endif /* STM32MP_USE_STM32IMAGE */
/*******************************************************************************
* CHIP ID
******************************************************************************/
@ -111,26 +117,6 @@ enum ddr_type {
(STM32MP_PARAM_LOAD_SIZE + \
STM32MP_HEADER_SIZE))
#ifdef AARCH32_SP_OPTEE
#define STM32MP_BL32_SIZE U(0)
#define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE
#define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \
STM32MP_OPTEE_BASE)
#else
#define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */
#endif
#define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL32_SIZE)
#define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */
#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
STM32MP_BL2_SIZE)
/* BL2 and BL32/sp_min require 4 tables */
#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
@ -141,38 +127,13 @@ enum ddr_type {
#if defined(IMAGE_BL2)
#define MAX_MMAP_REGIONS 11
#endif
#if defined(IMAGE_BL32)
#define MAX_MMAP_REGIONS 6
#endif
/* DTB initialization value */
#define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
STM32MP_DTB_SIZE)
#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
#define STM32MP_BL33_MAX_SIZE U(0x400000)
/* Define maximum page size for NAND devices */
#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
/*******************************************************************************
* STM32MP1 RAW partition offset for MTD devices
******************************************************************************/
#define STM32MP_NOR_BL33_OFFSET U(0x00080000)
#ifdef AARCH32_SP_OPTEE
#define STM32MP_NOR_TEEH_OFFSET U(0x00280000)
#define STM32MP_NOR_TEED_OFFSET U(0x002C0000)
#define STM32MP_NOR_TEEX_OFFSET U(0x00300000)
#endif
#define STM32MP_NAND_BL33_OFFSET U(0x00200000)
#ifdef AARCH32_SP_OPTEE
#define STM32MP_NAND_TEEH_OFFSET U(0x00600000)
#define STM32MP_NAND_TEED_OFFSET U(0x00680000)
#define STM32MP_NAND_TEEX_OFFSET U(0x00700000)
#endif
/*******************************************************************************
* STM32MP1 device/io map related constants (used for MMU)
******************************************************************************/

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@ -0,0 +1,61 @@
/*
* Copyright (C) 2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_FIP_DEF_H
#define STM32MP1_FIP_DEF_H
#define STM32MP_BL2_SIZE U(0x0001B000) /* 108 KB for BL2 */
#define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
#define STM32MP_BL32_SIZE U(0x00019000) /* 100 KB for BL32 */
#define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */
#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
STM32MP_BL2_DTB_SIZE)
#define STM32MP_BL32_DTB_BASE STM32MP_SYSRAM_BASE
#define STM32MP_BL32_BASE (STM32MP_BL32_DTB_BASE + \
STM32MP_BL32_DTB_SIZE)
#if defined(IMAGE_BL2)
#define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE
#define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
#endif
#if defined(IMAGE_BL32)
#define STM32MP_DTB_SIZE STM32MP_BL32_DTB_SIZE
#define STM32MP_DTB_BASE STM32MP_BL32_DTB_BASE
#endif
#ifdef AARCH32_SP_OPTEE
#define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE
#define STM32MP_OPTEE_SIZE (STM32MP_BL2_DTB_BASE - \
STM32MP_OPTEE_BASE)
#endif
#define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
STM32MP_BL33_MAX_SIZE)
/*
* MAX_MMAP_REGIONS is usually:
* BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
*/
#if defined(IMAGE_BL32)
#define MAX_MMAP_REGIONS 10
#endif
/*******************************************************************************
* STM32MP1 RAW partition offset for MTD devices
******************************************************************************/
#define STM32MP_NOR_FIP_OFFSET U(0x00080000)
#define STM32MP_NAND_FIP_OFFSET U(0x00200000)
#endif /* STM32MP1_FIP_DEF_H */

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@ -0,0 +1,65 @@
/*
* Copyright (C) 2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef STM32MP1_STM32IMAGE_DEF_H
#define STM32MP1_STM32IMAGE_DEF_H
#define STM32MP_BL2_SIZE U(0x0001C000) /* 112 KB for BL2 */
#define STM32MP_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
#ifdef AARCH32_SP_OPTEE
#define STM32MP_BL32_BASE STM32MP_SEC_SYSRAM_BASE
#define STM32MP_BL2_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE)
/* OP-TEE loads from SYSRAM base to BL2 DTB start address */
#define STM32MP_OPTEE_BASE STM32MP_BL32_BASE
#define STM32MP_OPTEE_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL2_SIZE - STM32MP_DTB_SIZE)
#define STM32MP_BL32_SIZE STM32MP_OPTEE_SIZE
#else /* AARCH32_SP_OPTEE */
#define STM32MP_BL32_SIZE U(0x00019000) /* 96 KB for BL32 */
#define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \
STM32MP_SEC_SYSRAM_SIZE - \
STM32MP_BL32_SIZE)
#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
STM32MP_BL2_SIZE)
#endif /* AARCH32_SP_OPTEE */
/* DTB initialization value */
#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
STM32MP_DTB_SIZE)
/*
* MAX_MMAP_REGIONS is usually:
* BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
*/
#if defined(IMAGE_BL32)
#define MAX_MMAP_REGIONS 6
#endif
/*******************************************************************************
* STM32MP1 RAW partition offset for MTD devices
******************************************************************************/
#define STM32MP_NOR_BL33_OFFSET U(0x00080000)
#ifdef AARCH32_SP_OPTEE
#define STM32MP_NOR_TEEH_OFFSET U(0x00280000)
#define STM32MP_NOR_TEED_OFFSET U(0x002C0000)
#define STM32MP_NOR_TEEX_OFFSET U(0x00300000)
#endif
#define STM32MP_NAND_BL33_OFFSET U(0x00200000)
#ifdef AARCH32_SP_OPTEE
#define STM32MP_NAND_TEEH_OFFSET U(0x00600000)
#define STM32MP_NAND_TEED_OFFSET U(0x00680000)
#define STM32MP_NAND_TEEX_OFFSET U(0x00700000)
#endif
#endif /* STM32MP1_STM32IMAGE_DEF_H */