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Merge "errata: workaround for Neoverse V1 errata 1774420" into integration
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commit
1d24eb33c5
@ -325,6 +325,10 @@ For Neoverse N1, the following errata build flags are defined :
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For Neoverse V1, the following errata build flags are defined :
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- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1
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CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
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in r1p1.
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- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1
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CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
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in r1p1.
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@ -13,6 +13,7 @@
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
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* Copyright (c) 2019-2021, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -21,6 +21,34 @@
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#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Neoverse V1 Errata #1774420.
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* This applies to revisions r0p0 and r1p0, fixed in r1p1.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_neoverse_v1_1774420_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1774420
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cbz x0, 1f
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/* Set bit 53 in CPUECTLR_EL1 */
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mrs x1, NEOVERSE_V1_CPUECTLR_EL1
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orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53
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msr NEOVERSE_V1_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_neoverse_v1_1774420_wa
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func check_errata_1774420
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/* Applies to r0p0 and r1p0. */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1774420
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/* --------------------------------------------------
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* Errata Workaround for Neoverse V1 Errata #1791573.
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* This applies to revisions r0p0 and r1p0, fixed in r1p1.
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@ -35,9 +63,9 @@ func errata_neoverse_v1_1791573_wa
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cbz x0, 1f
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/* Set bit 2 in ACTLR2_EL1 */
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mrs x1, NEOVERSE_V1_ACTLR2_EL1
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mrs x1, NEOVERSE_V1_ACTLR2_EL1
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orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2
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msr NEOVERSE_V1_ACTLR2_EL1, x1
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msr NEOVERSE_V1_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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@ -134,6 +162,7 @@ func neoverse_v1_errata_report
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_V1_1774420, neoverse_v1, 1774420
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report_errata ERRATA_V1_1791573, neoverse_v1, 1791573
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report_errata ERRATA_V1_1940577, neoverse_v1, 1940577
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@ -149,6 +178,11 @@ func neoverse_v1_reset_func
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msr SSBS, xzr
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isb
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#if ERRATA_V1_1774420
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mov x0, x18
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bl errata_neoverse_v1_1774420_wa
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#endif
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#if ERRATA_V1_1791573
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mov x0, x18
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bl errata_neoverse_v1_1791573_wa
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@ -372,6 +372,10 @@ ERRATA_N1_1868343 ?=0
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# exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround.
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ERRATA_N1_1946160 ?=0
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# Flag to apply erratum 1774420 workaround during reset. This erratum applies
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# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1.
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ERRATA_V1_1774420 ?=0
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# Flag to apply erratum 1791573 workaround during reset. This erratum applies
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# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1.
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ERRATA_V1_1791573 ?=0
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@ -685,6 +689,10 @@ $(eval $(call add_define,ERRATA_N1_1868343))
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$(eval $(call assert_boolean,ERRATA_N1_1946160))
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$(eval $(call add_define,ERRATA_N1_1946160))
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# Process ERRATA_V1_1774420 flag
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$(eval $(call assert_boolean,ERRATA_V1_1774420))
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$(eval $(call add_define,ERRATA_V1_1774420))
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# Process ERRATA_V1_1791573 flag
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$(eval $(call assert_boolean,ERRATA_V1_1791573))
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$(eval $(call add_define,ERRATA_V1_1791573))
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