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Merge pull request #1160 from davidcunado-arm/dc/fp_regs

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Move FPEXC32_EL2 to FP Context
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davidcunado-arm 2017-11-17 12:18:22 +00:00 committed by GitHub
commit 203444c500
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4 changed files with 18 additions and 15 deletions
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8
bl31/aarch64/crash_reporting.S
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@ -46,8 +46,7 @@ non_el3_sys_regs:
"tpidrro_el0", "dacr32_el2", "ifsr32_el2", "par_el1",\
"mpidr_el1", "afsr0_el1", "afsr1_el1", "contextidr_el1",\
"vbar_el1", "cntp_ctl_el0", "cntp_cval_el0", "cntv_ctl_el0",\
"cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0",\
"isr_el1", ""
"cntv_cval_el0", "cntkctl_el1", "sp_el0", "isr_el1", ""
panic_msg:
.asciz "PANIC in EL3 at x30 = 0x"
@ -313,9 +312,8 @@ func do_crash_reporting
mrs x15, cntv_cval_el0
bl str_in_crash_buf_print
mrs x8, cntkctl_el1
mrs x9, fpexc32_el2
mrs x10, sp_el0
mrs x11, isr_el1
mrs x9, sp_el0
mrs x10, isr_el1
bl str_in_crash_buf_print
/* Get the cpu specific registers to report */

1
docs/firmware-design.rst
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@ -1144,7 +1144,6 @@ The sample crash output is shown below.
cntv_ctl_el0 :0x0000000000000000
cntv_cval_el0 :0x0000000000000000
cntkctl_el1 :0x0000000000000000
fpexc32_el2 :0x0000000004000700
sp_el0 :0x0000000004010780
Guidelines for Reset Handlers

10
include/lib/el3_runtime/aarch64/context.h
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@ -100,8 +100,7 @@
#define CTX_SPSR_FIQ U(0xd8)
#define CTX_DACR32_EL2 U(0xe0)
#define CTX_IFSR32_EL2 U(0xe8)
#define CTX_FP_FPEXC32_EL2 U(0xf0)
#define CTX_TIMER_SYSREGS_OFF U(0x100) /* Align to the next 16 byte boundary */
#define CTX_TIMER_SYSREGS_OFF U(0xf0) /* Align to the next 16 byte boundary */
#else
#define CTX_TIMER_SYSREGS_OFF U(0xc0) /* Align to the next 16 byte boundary */
#endif /* __CTX_INCLUDE_AARCH32_REGS__ */
@ -161,7 +160,12 @@
#define CTX_FP_Q31 U(0x1f0)
#define CTX_FP_FPSR U(0x200)
#define CTX_FP_FPCR U(0x208)
#define CTX_FPREGS_END U(0x210)
#if CTX_INCLUDE_AARCH32_REGS
#define CTX_FP_FPEXC32_EL2 U(0x210)
#define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */
#else
#define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */
#endif
#endif
#ifndef __ASSEMBLY__

14
lib/el3_runtime/aarch64/context.S
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@ -90,9 +90,6 @@ func el1_sysregs_context_save
mrs x15, dacr32_el2
mrs x16, ifsr32_el2
stp x15, x16, [x0, #CTX_DACR32_EL2]
mrs x17, fpexc32_el2
str x17, [x0, #CTX_FP_FPEXC32_EL2]
#endif
/* Save NS timer registers if the build has instructed so */
@ -212,9 +209,6 @@ func el1_sysregs_context_restore
ldp x15, x16, [x0, #CTX_DACR32_EL2]
msr dacr32_el2, x15
msr ifsr32_el2, x16
ldr x17, [x0, #CTX_FP_FPEXC32_EL2]
msr fpexc32_el2, x17
#endif
/* Restore NS timer registers if the build has instructed so */
#if NS_TIMER_SWITCH
@ -275,6 +269,10 @@ func fpregs_context_save
mrs x10, fpcr
str x10, [x0, #CTX_FP_FPCR]
#if CTX_INCLUDE_AARCH32_REGS
mrs x11, fpexc32_el2
str x11, [x0, #CTX_FP_FPEXC32_EL2]
#endif
ret
endfunc fpregs_context_save
@ -318,6 +316,10 @@ func fpregs_context_restore
ldr x10, [x0, #CTX_FP_FPCR]
msr fpcr, x10
#if CTX_INCLUDE_AARCH32_REGS
ldr x11, [x0, #CTX_FP_FPEXC32_EL2]
msr fpexc32_el2, x11
#endif
/*
* No explict ISB required here as ERET to
* switch to secure EL1 or non-secure world