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Update change-log.rst for v1.5
Updated change-log.rst with summary of changes since release v1.4. Change-Id: I56b5a30d13a5a7099942535cbaeff0e2a5c5804e Signed-off-by: David Cunado <david.cunado@arm.com>
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David Cunado
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.. contents::
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Trusted Firmware-A - version 1.5
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================================
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New features
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------------
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- Added new firmware support to enable RAS (Reliability, Availability, and
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Serviceability) functionality.
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- Secure Partition Manager (SPM): A Secure Partition is a software execution
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environment instantiated in S-EL0 that can be used to implement simple
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management and security services. The SPM is the firmware component that
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is responsible for managing a Secure Partition.
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- SDEI dispatcher: Support for interrupt-based SDEI events and all
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interfaces as defined by the SDEI specification v1.0, see
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`SDEI Specification`_
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- Exception Handling Framework (EHF): Framework that allows dispatching of
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EL3 interrupts to their registered handlers which are registered based on
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their priorities. Facilitates firmware-first error handling policy where
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asynchronous exceptions may be routed to EL3.
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Integrated the TSPD with EHF.
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- Updated PSCI support:
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- Implemented PSCI v1.1 optional features `MEM_PROTECT` and `SYSTEM_RESET2`.
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The supported PSCI version was updated to v1.1.
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- Improved PSCI STAT timestamp collection, including moving accounting for
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retention states to be inside the locks and fixing handling of wrap-around
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when calculating residency in AArch32 execution state.
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- Added optional handler for early suspend that executes when suspending to
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a power-down state and with data caches enabled.
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This may provide a performance improvement on platforms where it is safe
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to perform some or all of the platform actions from `pwr_domain_suspend`
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with the data caches enabled.
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- Enabled build option, BL2_AT_EL3, for BL2 to allow execution at EL3 without
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any dependency on TF BL1.
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This allows platforms which already have a non-TF Boot ROM to directly load
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and execute BL2 and subsequent BL stages without need for BL1. This was not
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previously possible because BL2 executes at S-EL1 and cannot jump straight to
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EL3.
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- Implemented support for SMCCC v1.1, including `SMCCC_VERSION` and
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`SMCCC_ARCH_FEATURES`.
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Additionally, added support for `SMCCC_VERSION` in PSCI features to enable
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discovery of the SMCCC version via PSCI feature call.
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- Added Dynamic Configuration framework which enables each of the boot loader
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stages to be dynamically configured at runtime if required by the platform.
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The boot loader stage may optionally specify a firmware configuration file
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and/or hardware configuration file that can then be shared with the next boot
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loader stage.
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Introduced a new BL handover interface that essentially allows passing of 4
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arguments between the different BL stages.
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Updated cert_create and fip_tool to support the dynamic configuration files.
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The COT also updated to support these new files.
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- Code hygiene changes and alignment with MISRA guideline:
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- Fix use of undefined macros.
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- Achieved compliance with Mandatory MISRA coding rules.
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- Achieved compliance for following Required MISRA rules for the default
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build configurations on FVP and Juno platforms : 7.3, 8.3, 8.4, 8.5 and
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8.8.
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- Added support for Armv8.2-A architectural features:
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- Updated translation table set-up to set the CnP (Common not Private) bit
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for secure page tables so that multiple PEs in the same Inner Shareable
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domain can use the same translation table entries for a given stage of
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translation in a particular translation regime.
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- Extended the supported values of ID_AA64MMFR0_EL1.PARange to include the
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52-bit Physical Address range.
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- Added support for the Scalable Vector Extension to allow Normal world
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software to access SVE functionality but disable access to SVE, SIMD and
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floating point functionality from the Secure world in order to prevent
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corruption of the Z-registers.
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- Added support for Armv8.4-A architectural feature Activity Monitor Unit (AMU)
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extensions.
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In addition to the v8.4 architectural extension, AMU support on Cortex-A75
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was implemented.
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- Enhanced OP-TEE support to enable use of pageable OP-TEE image. The Arm
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standard platforms are updated to load up to 3 images for OP-TEE; header,
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pager image and paged image.
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The chain of trust is extended to support the additional images.
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- Enhancements to the translation table library:
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- Introduced APIs to get and set the memory attributes of a region.
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- Added support to manage both priviledge levels in translation regimes that
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describe translations for 2 Exception levels, specifically the EL1&0
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translation regime, and extended the memory map region attributes to
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include specifying Non-privileged access.
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- Added support to specify the granularity of the mappings of each region,
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for instance a 2MB region can be specified to be mapped with 4KB page
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tables instead of a 2MB block.
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- Disabled the higher VA range to avoid unpredictable behaviour if there is
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an attempt to access addresses in the higher VA range.
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- Added helpers for Device and Normal memory MAIR encodings that align with
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the Arm Architecture Reference Manual for Armv8-A (Arm DDI0487B.b).
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- Code hygiene including fixing type length and signedness of constants,
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refactoring of function to enable the MMU, removing all instances where
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the virtual address space is hardcoded and added comments that document
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alignment needed between memory attributes and attributes specified in
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TCR_ELx.
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- Updated GIC support:
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- Introduce new APIs for GICv2 and GICv3 that provide the capability to
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specify interrupt properties rather than list of interrupt numbers alone.
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The Arm platforms and other upstream platforms are migrated to use
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interrupt properties.
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- Added helpers to save / restore the GICv3 context, specifically the
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Distributor and Redistributor contexts and architectural parts of the ITS
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power management. The Distributor and Redistributor helpers also support
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the implementation-defined part of GIC-500 and GIC-600.
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Updated the Arm FVP platform to save / restore the GICv3 context on system
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suspend / resume as an example of how to use the helpers.
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Introduced a new TZC secured DDR carve-out for use by Arm platforms for
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storing EL3 runtime data such as the GICv3 register context.
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- Added support for Armv7-A architecture via build option ARM_ARCH_MAJOR=7.
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This includes following features:
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- Updates GICv2 driver to manage GICv1 with security extensions.
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- Software implementation for 32bit division.
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- Enabled use of generic timer for platforms that do not set
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ARM_CORTEX_Ax=yes.
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- Support for Armv7-A Virtualization extensions [DDI0406C_C].
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- Support for both Armv7-A platforms that only have 32-bit addressing and
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Armv7-A platforms that support large page addressing.
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- Included support for following Armv7 CPUs: Cortex-A12, Cortex-A17,
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Cortex-A7, Cortex-A5, Cortex-A9, Cortex-A15.
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- Added support in QEMU for Armv7-A/Cortex-A15.
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- Enhancements to Firmware Update feature:
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- Updated the FWU documentation to describe the additional images needed for
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Firmware update, and how they are used for both the Juno platform and the
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Arm FVP platforms.
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- Enhancements to Trusted Board Boot feature:
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- Added support to cert_create tool for RSA PKCS1# v1.5 and SHA384, SHA512
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and SHA256.
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- For Arm platforms added support to use ECDSA keys.
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- Enhanced the mbed TLS wrapper layer to include support for both RSA and
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ECDSA to enable runtime selection between RSA and ECDSA keys.
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- Added support for secure interrupt handling in AArch32 sp_min, hardcoded to
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only handle FIQs.
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- Added support to allow a platform to load images from multiple boot sources,
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for example from a second flash drive.
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- Added a logging framework that allows platforms to reduce the logging level
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at runtime and additionally the prefix string can be defined by the platform.
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- Further improvements to register initialisation:
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- Control register PMCR_EL0 / PMCR is set to prohibit cycle counting in the
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secure world. This register is added to the list of registers that are
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saved and restored during world switch.
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- When EL3 is running in AArch32 execution state, the Non-secure version of
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SCTLR is explicitly initialised during the warmboot flow rather than
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relying on the hardware to set the correct reset values.
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- Enhanced support for Arm platforms:
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- Introduced driver for Shared-Data-Structure (SDS) framework which is used
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for communication between SCP and the AP CPU, replacing Boot-Over_MHU
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(BOM) protocol.
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The Juno platform is migrated to use SDS with the SCMI support added in
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v1.3 and is set as default.
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The driver can be found in the plat/arm/css/drivers folder.
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- Improved memory usage by only mapping TSP memory region when the TSPD has
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been included in the build. This reduces the memory footprint and avoids
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unnecessary memory being mapped.
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- Updated support for multi-threading CPUs for FVP platforms - always check
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the MT field in MPDIR and access the bit fields accordingly.
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- Support building for platforms that model DynamIQ configuration by
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implementing all CPUs in a single cluster.
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- Improved nor flash driver, for instance clearing status registers before
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sending commands. Driver can be found plat/arm/board/common folder.
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- Enhancements to QEMU platform:
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- Added support for TBB.
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- Added support for using OP-TEE pageable image.
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- Added support for LOAD_IMAGE_V2.
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- Migrated to use translation table library v2 by default.
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- Added support for SEPARATE_CODE_AND_RODATA.
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- Applied workarounds CVE-2017-5715 on Arm Cortex-A57, -A72, -A73 and -A75, and
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for Armv7-A CPUs Cortex-A9, -A15 and -A17.
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- Applied errata workaround for Arm Cortex-A57: 859972.
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- Applied errata workaround for Arm Cortex-A72: 859971.
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- Added support for Poplar 96Board platform.
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- Added support for Raspberry Pi 3 platform.
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- Added Call Frame Information (CFI) assembler directives to the vector entries
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which enables debuggers to display the backtrace of functions that triggered
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a synchronous abort.
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- Added ability to build dtb.
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- Added support for pre-tool (cert_create and fiptool) image processing
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enabling compression of the image files before processing by cert_create and
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fiptool.
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This can reduce fip size and may also speed up loading of images. The image
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verification will also get faster because certificates are generated based on
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compressed images.
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Imported zlib 1.2.11 to implement gunzip() for data compression.
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- Enhancements to fiptool:
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- Enabled the fiptool to be built using Visual Studio.
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- Added padding bytes at the end of the last image in the fip to be
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facilitate transfer by DMA.
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Issues resolved since last release
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----------------------------------
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- TF-A can be built with optimisations disabled (-O0).
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- Memory layout updated to enable Trusted Board Boot on Juno platform when
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running TF-A in AArch32 execution mode (resolving `tf-issue#501`_).
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Known Issues
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------------
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- DTB creation not supported when building on a windows host. This step in the
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build process is skipped when running on a windows host.
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Trusted Firmware-A - version 1.4
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================================
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@ -141,7 +427,7 @@ New features
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- Added version 2 of translation table library that allows different
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translation tables to be modified by using different 'contexts'. Version 1
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of the transalation table library only allows the current EL's translation
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of the translation table library only allows the current EL's translation
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tables to be modified.
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Version 2 of the translation table also added support for dynamic
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@ -285,7 +571,7 @@ Known Issues
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- Trusted Board Boot currently does not work on Juno when running Trusted
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Firmware in AArch32 execution state due to error when loading the sp_min to
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memory becasue of lack of free space available. See `tf-issue#501`_ for more
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memory because of lack of free space available. See `tf-issue#501`_ for more
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details.
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- The errata workaround for A53 errata 843419 is only available from binutils
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@ -1361,6 +1647,7 @@ releases of TF-A.
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*Copyright (c) 2013-2018, Arm Limited and Contributors. All rights reserved.*
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.. _SDEI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
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.. _PSCI Integration Guide: psci-lib-integration-guide.rst
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.. _Developer Certificate of Origin: ../dco.txt
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.. _Contribution Guide: ../contributing.rst
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