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qemu: Support SEPARATE_CODE_AND_RODATA
Update qemu_configure_mmu_##_el to add an additional region for code, marked as MT_CODE | MT_SECURE. Update ro region attributes to NON_EXEC. Update calls to QEMU_CONFIGURE_BLx_MMU() to pass an additional region for code. Update calls to pass regions defined in common_def.h. Increase MAX_MMAP_REGIONS to 10. Enable SEPARATE_CODE_AND_RODATA by default on QEMU builds. Fixes ARM-software/tf-issues#558 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
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@ -168,7 +168,7 @@
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_MMAP_REGIONS 8
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#define MAX_MMAP_REGIONS 10
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#define MAX_XLAT_TABLES 6
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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@ -167,6 +167,8 @@ ifneq ($(BL32_EXTRA2),)
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$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
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endif
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SEPARATE_CODE_AND_RODATA := 1
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# Disable the PSCI platform compatibility layer
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ENABLE_PLAT_COMPAT := 0
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@ -12,15 +12,6 @@
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#include <platform_def.h>
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#include "qemu_private.h"
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/*******************************************************************************
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* Declarations of linker defined symbols which will tell us where BL1 lives
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* in Trusted RAM
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******************************************************************************/
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extern uint64_t __BL1_RAM_START__;
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extern uint64_t __BL1_RAM_END__;
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#define BL1_RAM_BASE (uint64_t)(&__BL1_RAM_START__)
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#define BL1_RAM_LIMIT (uint64_t)(&__BL1_RAM_END__)
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/* Data structure which holds the extents of the trusted SRAM for BL1*/
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static meminfo_t bl1_tzram_layout;
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@ -67,7 +58,8 @@ void bl1_plat_arch_setup(void)
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{
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QEMU_CONFIGURE_BL1_MMU(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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BL1_RO_BASE, BL1_RO_LIMIT,
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BL_CODE_BASE, BL1_CODE_END,
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BL1_RO_DATA_BASE, BL1_RO_DATA_END,
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BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
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}
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@ -17,14 +17,6 @@
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#include <utils.h>
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#include "qemu_private.h"
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/*
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* The next 2 constants identify the extents of the code & RO data region.
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* These addresses are used by the MMU setup code and therefore they must be
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* page-aligned. It is the responsibility of the linker script to ensure that
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* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
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*/
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#define BL2_RO_BASE (unsigned long)(&__RO_START__)
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#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
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/* Data structure which holds the extents of the trusted SRAM for BL2 */
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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@ -192,7 +184,8 @@ void bl2_plat_arch_setup(void)
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{
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QEMU_CONFIGURE_BL2_MMU(bl2_tzram_layout.total_base,
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bl2_tzram_layout.total_size,
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BL2_RO_BASE, BL2_RO_LIMIT,
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BL_CODE_BASE, BL_CODE_END,
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BL_RO_DATA_BASE, BL_RO_DATA_END,
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BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
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}
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@ -19,8 +19,6 @@
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* script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
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* refer to page-aligned addresses.
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*/
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#define BL31_RO_BASE (unsigned long)(&__RO_START__)
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#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
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#define BL31_END (unsigned long)(&__BL31_END__)
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/*
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@ -108,8 +106,9 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void bl31_plat_arch_setup(void)
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{
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qemu_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE),
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BL31_RO_BASE, BL31_RO_LIMIT,
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qemu_configure_mmu_el3(BL31_BASE, (BL31_END - BL31_BASE),
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BL_CODE_BASE, BL_CODE_END,
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BL_RO_DATA_BASE, BL_RO_DATA_END,
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BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
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}
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@ -104,6 +104,8 @@ static const mmap_region_t plat_qemu_mmap[] = {
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#define DEFINE_CONFIGURE_MMU_EL(_el) \
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void qemu_configure_mmu_##_el(unsigned long total_base, \
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unsigned long total_size, \
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unsigned long code_start, \
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unsigned long code_limit, \
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unsigned long ro_start, \
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unsigned long ro_limit, \
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unsigned long coh_start, \
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@ -112,9 +114,12 @@ static const mmap_region_t plat_qemu_mmap[] = {
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mmap_add_region(total_base, total_base, \
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total_size, \
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MT_MEMORY | MT_RW | MT_SECURE); \
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mmap_add_region(code_start, code_start, \
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code_limit - code_start, \
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MT_CODE | MT_SECURE); \
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mmap_add_region(ro_start, ro_start, \
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ro_limit - ro_start, \
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MT_MEMORY | MT_RO | MT_SECURE); \
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MT_RO_DATA | MT_SECURE); \
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mmap_add_region(coh_start, coh_start, \
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coh_limit - coh_start, \
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MT_DEVICE | MT_RW | MT_SECURE); \
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@ -9,16 +9,22 @@
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#include <sys/types.h>
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#include <xlat_tables_defs.h>
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#include "../../bl1/bl1_private.h"
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void qemu_configure_mmu_secure(unsigned long total_base,
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unsigned long total_size,
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unsigned long code_start, unsigned long code_limit,
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unsigned long ro_start, unsigned long ro_limit,
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unsigned long coh_start, unsigned long coh_limit);
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void qemu_configure_mmu_el1(unsigned long total_base, unsigned long total_size,
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unsigned long code_start, unsigned long code_limit,
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unsigned long ro_start, unsigned long ro_limit,
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unsigned long coh_start, unsigned long coh_limit);
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void qemu_configure_mmu_el3(unsigned long total_base, unsigned long total_size,
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unsigned long code_start, unsigned long code_limit,
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unsigned long ro_start, unsigned long ro_limit,
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unsigned long coh_start, unsigned long coh_limit);
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