CTCaer/switch-l4t-atf
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fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit

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after this commit: If15cf3b9d3e2e7876c40ce888f22e887893fe696
plat/qemu/common/qemu_pm.c:116:	    (entrypoint < (NS_DRAM0_BASE + NS_DRAM0_SIZE)))
the above line (NS_DRAM0_BASE + NS_DRAM0_SIZE) = 0x100000000, which will
overflow 32bit and cause ERROR
SO add ULL to fix it

tested on compiler:
gcc version 10.2.1 20201103 (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16))

Signed-off-by: Darren Liang <lwp513@qq.com>
Change-Id: I1d769b0803142d37bd2968d765ab04a9c7c5c21a
This commit is contained in:
lwpDarren 2021-08-18 00:54:19 +08:00 committed by lwp513
parent 391828923f
commit 325716c97b
1 changed files with 2 additions and 2 deletions
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4
plat/qemu/qemu/include/platform_def.h
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@ -80,8 +80,8 @@
#define SEC_ROM_BASE 0x00000000
#define SEC_ROM_SIZE 0x00020000
#define NS_DRAM0_BASE 0x40000000
#define NS_DRAM0_SIZE 0xc0000000
#define NS_DRAM0_BASE ULL(0x40000000)
#define NS_DRAM0_SIZE ULL(0xc0000000)
#define SEC_SRAM_BASE 0x0e000000
#define SEC_SRAM_SIZE 0x00060000