CTCaer/switch-l4t-atf
1
0
Fork 0
mirror of https://github.com/CTCaer/switch-l4t-atf.git synced 2024-12-13 13:15:39 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Set processor endianness immediately after RESET

Browse Source 
SCTLR_EL3.EE is being configured too late in bl1_arch_setup() and
bl31_arch_setup() after data accesses have already occured on
the cold and warm boot paths.

This control bit must be configured immediately on CPU reset to
match the endian state of the firmware (little endian).

Fixes ARM-software/tf-issues#145

Change-Id: Ie12e46fbbed6baf024c30beb50751591bb8c8655
This commit is contained in:
Andrew Thoelke 2014-04-24 15:33:24 +01:00
parent e404d7f44a
commit 40fd072548
3 changed files with 12 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
bl1/aarch64/bl1_arch_setup.c
View File

@ -39,10 +39,9 @@ void bl1_arch_setup(void)
{
unsigned long tmp_reg = 0;
/* Enable alignment checks and set the exception endianess to LE */
/* Enable alignment checks */
tmp_reg = read_sctlr_el3();
tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT);
tmp_reg &= ~SCTLR_EE_BIT;
write_sctlr_el3(tmp_reg);
/*

10
bl1/aarch64/bl1_entrypoint.S
View File

@ -42,6 +42,16 @@
*/
func bl1_entrypoint
/* ---------------------------------------------
* Set the CPU endianness before doing anything
* that might involve memory reads or writes
* ---------------------------------------------
*/
mrs x0, sctlr_el3
bic x0, x0, #SCTLR_EE_BIT
msr sctlr_el3, x0
isb
/* ---------------------------------------------
* Perform any processor specific actions upon
* reset e.g. cache, tlb invalidations etc.

3
bl31/aarch64/bl31_arch_setup.c
View File

@ -45,10 +45,9 @@ void bl31_arch_setup(void)
unsigned long tmp_reg = 0;
uint64_t counter_freq;
/* Enable alignment checks and set the exception endianness to LE */
/* Enable alignment checks */
tmp_reg = read_sctlr_el3();
tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT);
tmp_reg &= ~SCTLR_EE_BIT;
write_sctlr_el3(tmp_reg);
/*