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zynqmp: Separate code and rodata

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Set the SEPARATE_CODE_AND_RODATA build flag to map read-only data as
execute never.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
This commit is contained in:
Soren Brinkmann 2016-07-08 14:45:14 -07:00
parent 91fad6551e
commit 47395a2321
4 changed files with 16 additions and 46 deletions
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31
plat/xilinx/zynqmp/bl31_zynqmp_setup.c
View File

@ -38,24 +38,7 @@
#include <platform.h>
#include "zynqmp_private.h"
/*
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
*/
extern unsigned long __RO_START__;
extern unsigned long __RO_END__;
extern unsigned long __COHERENT_RAM_START__;
extern unsigned long __COHERENT_RAM_END__;
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
@ -154,12 +137,12 @@ void bl31_plat_arch_setup(void)
plat_arm_interconnect_init();
plat_arm_interconnect_enter_coherency();
arm_setup_page_tables(BL31_RO_BASE,
BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
0,
0,
arm_setup_page_tables(BL31_BASE,
BL31_END - BL31_BASE,
BL_CODE_BASE,
BL_CODE_LIMIT,
BL_RO_DATA_BASE,
BL_RO_DATA_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
enable_mmu_el3(0);

2
plat/xilinx/zynqmp/include/platform_def.h
View File

@ -100,7 +100,7 @@
* Platform specific page table and MMU setup constants
******************************************************************************/
#define ADDR_SPACE_SIZE (1ull << 32)
#define MAX_MMAP_REGIONS 6
#define MAX_MMAP_REGIONS 7
#if IMAGE_BL32
# define MAX_XLAT_TABLES 5
#else

1
plat/xilinx/zynqmp/platform.mk
View File

@ -30,6 +30,7 @@ ENABLE_PLAT_COMPAT := 0
PROGRAMMABLE_RESET_ADDRESS := 1
PSCI_EXTENDED_STATE_ID := 1
A53_DISABLE_NON_TEMPORAL_HINT := 0
SEPARATE_CODE_AND_RODATA := 1
ifdef ZYNQMP_ATF_MEM_BASE
$(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))

28
plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
View File

@ -35,19 +35,8 @@
#include <plat_arm.h>
#include "../zynqmp_private.h"
/*
* The next 3 constants identify the extents of the code & RO data region and
* the limit of the BL32 image. These addresses are used by the MMU setup code
* and therefore they must be page-aligned. It is the responsibility of the
* linker script to ensure that __RO_START__, __RO_END__ & & __BL32_END__
* linker symbols refer to page-aligned addresses.
*/
#define BL32_RO_BASE (unsigned long)(&__RO_START__)
#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL32_END (unsigned long)(&__BL32_END__)
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
@ -57,7 +46,6 @@
*/
#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/*******************************************************************************
* Initialize the UART
@ -90,16 +78,14 @@ void tsp_platform_setup(void)
******************************************************************************/
void tsp_plat_arch_setup(void)
{
arm_setup_page_tables(BL32_RO_BASE,
(BL32_END - BL32_RO_BASE),
BL32_RO_BASE,
BL32_RO_LIMIT,
0,
0
#if USE_COHERENT_MEM
, BL32_COHERENT_RAM_BASE,
arm_setup_page_tables(BL32_BASE,
BL32_END - BL32_BASE,
BL_CODE_BASE,
BL_CODE_LIMIT,
BL_RO_DATA_BASE,
BL_RO_DATA_LIMIT,
BL32_COHERENT_RAM_BASE,
BL32_COHERENT_RAM_LIMIT
#endif
);
enable_mmu_el1(0);
}