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https://github.com/CTCaer/switch-l4t-atf.git
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feat(plat/mdeiatek/mt8192): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9c7af9a4f75216ed2c6b44458d121a352bef4b95
This commit is contained in:
Rex-BC Chen
Rex-BC Chen
parent
d1987f4c8f
commit
5183e637a0
139
plat/mediatek/mt8192/drivers/dfd/plat_dfd.c
Normal file
139
plat/mediatek/mt8192/drivers/dfd/plat_dfd.c
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@ -0,0 +1,139 @@
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/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <mtk_sip_svc.h>
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#include <plat_dfd.h>
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static bool dfd_enabled;
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static uint64_t dfd_base_addr;
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static uint64_t dfd_chain_length;
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static uint64_t dfd_cache_dump;
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static void dfd_setup(uint64_t base_addr, uint64_t chain_length,
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uint64_t cache_dump)
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{
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/* bit[0]: rg_rw_dfd_internal_dump_en -> 1 */
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/* bit[2]: rg_rw_dfd_clock_stop_en -> 1 */
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sync_writel(DFD_INTERNAL_CTL, 0x5);
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/* bit[13]: xreset_b_update_disable */
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13);
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/*
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* bit[10:3]: DFD trigger selection mask
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* bit[3]: rg_rw_dfd_trigger_sel[0] = 1(enable wdt trigger)
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* bit[4]: rg_rw_dfd_trigger_sel[1] = 1(enable HW trigger)
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* bit[5]: rg_rw_dfd_trigger_sel[2] = 1(enable SW trigger)
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* bit[6]: rg_rw_dfd_trigger_sel[3] = 1(enable SW non-security trigger)
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* bit[7]: rg_rw_dfd_trigger_sel[4] = 1(enable timer trigger)
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*/
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 3);
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/* bit[20:19]: rg_dfd_armpll_div_mux_sel switch to PLL2 for DFD */
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19);
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/*
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* bit[0]: rg_rw_dfd_auto_power_on = 1
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* bit[2:1]: rg_rw_dfd_auto_power_on_dely = 1(10us)
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* bit[4:2]: rg_rw_dfd_power_on_wait_time = 1(20us)
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*/
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mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB);
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/* longest scan chain length */
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mmio_write_32(DFD_CHAIN_LENGTH0, chain_length);
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/* bit[1:0]: rg_rw_dfd_shift_clock_ratio */
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mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0);
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/* rg_dfd_test_so_over_64 */
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mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1);
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/* DFD3.0 */
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mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_DIS_VAL);
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mmio_write_32(DFD_TEST_SI_1, DFD_TEST_SI_1_VAL);
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mmio_write_32(DFD_TEST_SI_2, DFD_TEST_SI_2_VAL);
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mmio_write_32(DFD_TEST_SI_3, DFD_TEST_SI_3_VAL);
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/* for iLDO feature */
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sync_writel(DFD_POWER_CTL, 0xF9);
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/* set base address */
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mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24);
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/*
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* disable sleep protect of DFD
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* 10001220[8]: protect_en_reg[8]
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* 10001a3c[2]: infra_mcu_pwr_ctl_mask[2]
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*/
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mmio_clrbits_32(DFD_O_PROTECT_EN_REG, 1 << 8);
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mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, 1 << 2);
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/* clean DFD trigger status */
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sync_writel(DFD_CLEAN_STATUS, 0x1);
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sync_writel(DFD_CLEAN_STATUS, 0x0);
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/* DFD-3.0 */
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sync_writel(DFD_V30_CTL, 0x1);
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/* setup global variables for suspend and resume */
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dfd_enabled = true;
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dfd_base_addr = base_addr;
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dfd_chain_length = chain_length;
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dfd_cache_dump = cache_dump;
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if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
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/* DFD3.5 */
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mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_EN_VAL);
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sync_writel(DFD_V35_ENALBE, 0x1);
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sync_writel(DFD_V35_TAP_NUMBER, 0xB);
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sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
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sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
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if (cache_dump & DFD_PARITY_ERR_TRIGGER) {
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sync_writel(DFD_HW_TRIGGER_MASK, 0xC);
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mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4);
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}
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}
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dsbsy();
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}
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void dfd_resume(void)
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{
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if (dfd_enabled == true) {
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dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
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}
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}
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uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
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uint64_t arg2, uint64_t arg3)
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{
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uint64_t ret = 0L;
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switch (arg0) {
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case PLAT_MTK_DFD_SETUP_MAGIC:
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dfd_setup(arg1, arg2, arg3);
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break;
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case PLAT_MTK_DFD_READ_MAGIC:
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/* only allow to access DFD register base + 0x200 */
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if (arg1 <= 0x200) {
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ret = mmio_read_32(MISC1_CFG_BASE + arg1);
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}
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break;
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case PLAT_MTK_DFD_WRITE_MAGIC:
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/* only allow to access DFD register base + 0x200 */
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if (arg1 <= 0x200) {
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sync_writel(MISC1_CFG_BASE + arg1, arg2);
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}
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break;
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default:
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ret = MTK_SIP_E_INVALID_PARAM;
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break;
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}
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return ret;
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}
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70
plat/mediatek/mt8192/drivers/dfd/plat_dfd.h
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70
plat/mediatek/mt8192/drivers/dfd/plat_dfd.h
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@ -0,0 +1,70 @@
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/*
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* Copyright (c) 2021, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_DFD_H
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#define PLAT_DFD_H
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#include <arch_helpers.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \
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dsbsy(); \
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} while (0)
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#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150)
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#define PLAT_MTK_DFD_READ_MAGIC (0x99716151)
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#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152)
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#define MCU_BIU_BASE (MCUCFG_BASE)
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#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040)
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#define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)
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#define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)
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#define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)
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#define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)
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#define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)
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#define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20)
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#define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24)
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#define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)
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#define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)
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#define DFD_INTERNAL_TEST_SO_OVER_64 (MISC1_CFG_BASE + 0x34)
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#define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)
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#define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C)
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#define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50)
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#define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)
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#define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)
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#define DFD_CLEAN_STATUS (MISC1_CFG_BASE + 0x60)
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#define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8)
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#define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC)
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#define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC)
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#define DFD_V35_ENALBE (MCU_BIU_BASE + 0xE0A8)
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#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC)
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#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0)
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#define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4)
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#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0)
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#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4)
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#define DFD_O_PROTECT_EN_REG (0x10001220)
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#define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C)
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#define DFD_O_SET_BASEADDR_REG (0x10043034)
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#define DFD_CACHE_DUMP_ENABLE 1U
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#define DFD_PARITY_ERR_TRIGGER 2U
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#define DFD_TEST_SI_0_CACHE_DIS_VAL (0x1E000202)
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#define DFD_TEST_SI_0_CACHE_EN_VAL (0x1E000002)
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#define DFD_TEST_SI_1_VAL (0x20408100)
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#define DFD_TEST_SI_2_VAL (0x10101000)
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#define DFD_TEST_SI_3_VAL (0x00000010)
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#define DFD_V35_TAP_EN_VAL (0x43FF)
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#define DFD_V35_SEQ0_0_VAL (0x63668820)
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void dfd_resume(void);
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uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
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uint64_t arg2, uint64_t arg3);
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#endif /* PLAT_DFD_H */
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@ -10,6 +10,10 @@
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/*******************************************************************************
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* Plat SiP function constants
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******************************************************************************/
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#define MTK_PLAT_SIP_NUM_CALLS 0
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#define MTK_PLAT_SIP_NUM_CALLS 2
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/* DFD */
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#define MTK_SIP_KERNEL_DFD_AARCH32 0x82000205
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#define MTK_SIP_KERNEL_DFD_AARCH64 0xC2000205
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#endif /* PLAT_SIP_CALLS_H */
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@ -17,6 +17,7 @@
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#include <mtk_ptp3_common.h>
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#include <mtspmc.h>
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#include <plat/common/platform.h>
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#include <plat_dfd.h>
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#include <plat_mtk_lpm.h>
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#include <plat_params.h>
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#include <plat_pm.h>
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@ -168,6 +169,8 @@ static void plat_mcusys_pwron_common(unsigned int cpu,
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mt_gic_distif_restore();
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gic_sgi_restore_all();
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dfd_resume();
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plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state);
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}
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@ -9,6 +9,7 @@
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#include <mtk_apusys.h>
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#include <mtk_sip_svc.h>
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#include <mt_spm_vcorefs.h>
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#include <plat_dfd.h>
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#include "plat_sip_calls.h"
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uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
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@ -34,6 +35,11 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
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ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0);
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SMC_RET2(handle, ret, rnd_val0);
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break;
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case MTK_SIP_KERNEL_DFD_AARCH32:
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case MTK_SIP_KERNEL_DFD_AARCH64:
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ret = dfd_smc_dispatcher(x1, x2, x3, x4);
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SMC_RET1(handle, ret);
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break;
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default:
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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break;
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@ -19,6 +19,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
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-I${MTK_PLAT_SOC}/drivers/apusys/ \
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-I${MTK_PLAT_SOC}/drivers/dcm \
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-I${MTK_PLAT_SOC}/drivers/devapc \
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-I${MTK_PLAT_SOC}/drivers/dfd \
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-I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
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-I${MTK_PLAT_SOC}/drivers/gpio/ \
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-I${MTK_PLAT_SOC}/drivers/mcdi/ \
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@ -68,6 +69,7 @@ BL31_SOURCES += common/desc_image_load.c \
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${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
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${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
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${MTK_PLAT_SOC}/drivers/devapc/devapc.c \
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${MTK_PLAT_SOC}/drivers/dfd/plat_dfd.c \
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${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
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${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
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${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
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