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Tegra194: mce: remove unused NVG functions

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This patch removes unused functions from the NVG driver.

* nvg_enable_power_perf_mode
* nvg_disable_power_perf_mode
* nvg_enable_power_saver_modes
* nvg_disable_power_saver_modes
* nvg_roc_clean_cache
* nvg_roc_flush_cache

Change-Id: I0387a40dec35686deaad623a8350de89acfe9393
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2018-05-14 15:54:59 -07:00
parent 54990e377c
commit 532df95630
2 changed files with 6 additions and 99 deletions
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15
plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
View File

@ -45,10 +45,6 @@
/* declarations for NVG handler functions */
uint64_t nvg_get_version(void);
int32_t nvg_enable_power_perf_mode(void);
int32_t nvg_disable_power_perf_mode(void);
int32_t nvg_enable_power_saver_modes(void);
int32_t nvg_disable_power_saver_modes(void);
void nvg_set_wake_time(uint32_t wake_time);
void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask);
@ -57,19 +53,20 @@ uint64_t nvg_get_cstate_stat_query_value(void);
int32_t nvg_is_sc7_allowed(void);
int32_t nvg_online_core(uint32_t core);
int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
int32_t nvg_roc_clean_cache(void);
int32_t nvg_roc_flush_cache(void);
int32_t nvg_roc_clean_cache_trbits(void);
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
int32_t nvg_roc_clean_cache_trbits(void);
void nvg_enable_strict_checking_mode(void);
void nvg_system_shutdown(void);
void nvg_system_reboot(void);
/* declarations for assembly functions */
void nvg_set_request_data(uint64_t req, uint64_t data);
void nvg_set_request(uint64_t req);
uint64_t nvg_get_result(void);
uint64_t nvg_cache_clean(void);
uint64_t nvg_cache_clean_inval(void);
uint64_t nvg_cache_inval_all(void);
void nvg_enable_strict_checking_mode(void);
void nvg_system_shutdown(void);
void nvg_system_reboot(void);
/* MCE helper functions */
void mce_enable_strict_checking(void);

90
plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
View File

@ -30,54 +30,6 @@ uint64_t nvg_get_version(void)
return (uint64_t)nvg_get_result();
}
/*
* Enable the perf per watt mode.
*
* NVGDATA[0]: SW(RW), 1 = enable perf per watt mode
*/
int32_t nvg_enable_power_perf_mode(void)
{
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U);
return 0;
}
/*
* Disable the perf per watt mode.
*
* NVGDATA[0]: SW(RW), 0 = disable perf per watt mode
*/
int32_t nvg_disable_power_perf_mode(void)
{
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U);
return 0;
}
/*
* Enable the battery saver mode.
*
* NVGDATA[2]: SW(RW), 1 = enable battery saver mode
*/
int32_t nvg_enable_power_saver_modes(void)
{
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U);
return 0;
}
/*
* Disable the battery saver mode.
*
* NVGDATA[2]: SW(RW), 0 = disable battery saver mode
*/
int32_t nvg_disable_power_saver_modes(void)
{
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U);
return 0;
}
/*
* Set the expected wake time in TSC ticks for the next low-power state the
* core enters.
@ -197,48 +149,6 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
return ret;
}
/*
* Cache clean operation for all CCPLEX caches.
*/
int32_t nvg_roc_clean_cache(void)
{
int32_t ret = 0;
/* check if cache flush through mts is supported */
if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
if (nvg_cache_clean() == 0U) {
ERROR("%s: failed\n", __func__);
ret = -ENODEV;
}
} else {
ret = -ENOTSUP;
}
return ret;
}
/*
* Cache clean and invalidate operation for all CCPLEX caches.
*/
int32_t nvg_roc_flush_cache(void)
{
int32_t ret = 0;
/* check if cache flush through mts is supported */
if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
if (nvg_cache_clean_inval() == 0U) {
ERROR("%s: failed\n", __func__);
ret = -ENODEV;
}
} else {
ret = -ENOTSUP;
}
return ret;
}
/*
* Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches.
*/