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https://github.com/CTCaer/switch-l4t-atf.git
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qemu: Add support for Trusted Board Boot
This patch adds support for TBB to qemu. An RSA ROT keypair is generated at build time and is included into BL1/BL2. The key and content certificates are read over semihosting. Fixes ARM-software/tf-issues#526 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
This commit is contained in:
Michalis Pappas
parent
ccd0c24cf8
commit
5cc34b10b0
@ -13,6 +13,7 @@ ifeq ($(NEED_BL32),yes)
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$(eval $(call add_define,QEMU_LOAD_BL32))
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endif
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PLAT_PATH := plat/qemu/
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PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
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-Iinclude/plat/arm/common/aarch64/ \
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-Iplat/qemu/include \
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@ -36,6 +37,51 @@ include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
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endif
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ifneq (${TRUSTED_BOARD_BOOT},0)
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include drivers/auth/mbedtls/mbedtls_crypto.mk
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include drivers/auth/mbedtls/mbedtls_x509.mk
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USE_TBBR_DEFS := 1
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AUTH_SOURCES := drivers/auth/auth_mod.c \
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drivers/auth/crypto_mod.c \
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drivers/auth/img_parser_mod.c \
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drivers/auth/tbbr/tbbr_cot.c
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PLAT_INCLUDES += -Iinclude/bl1/tbbr
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BL1_SOURCES += ${AUTH_SOURCES} \
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bl1/tbbr/tbbr_img_desc.c \
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plat/common/tbbr/plat_tbbr.c \
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plat/qemu/qemu_trusted_boot.c \
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$(PLAT_PATH)/qemu_rotpk.S
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BL2_SOURCES += ${AUTH_SOURCES} \
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plat/common/tbbr/plat_tbbr.c \
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plat/qemu/qemu_trusted_boot.c \
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$(PLAT_PATH)/qemu_rotpk.S
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ROT_KEY = $(BUILD_PLAT)/rot_key.pem
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ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
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$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
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$(BUILD_PLAT)/bl1/qemu_rotpk.o: $(ROTPK_HASH)
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$(BUILD_PLAT)/bl2/qemu_rotpk.o: $(ROTPK_HASH)
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certificates: $(ROT_KEY)
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$(ROT_KEY):
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@echo " OPENSSL $@"
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$(Q)openssl genrsa 2048 > $@ 2>/dev/null
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$(ROTPK_HASH): $(ROT_KEY)
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@echo " OPENSSL $@"
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$(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
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openssl dgst -sha256 -binary > $@ 2>/dev/null
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endif
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BL1_SOURCES += drivers/io/io_semihosting.c \
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drivers/io/io_storage.c \
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drivers/io/io_fip.c \
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@ -26,14 +26,14 @@
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#define BL33_IMAGE_NAME "bl33.bin"
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#if TRUSTED_BOARD_BOOT
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#define BL2_CERT_NAME "bl2.crt"
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#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt"
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#define TRUSTED_KEY_CERT_NAME "trusted_key.crt"
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#define BL31_KEY_CERT_NAME "bl31_key.crt"
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#define BL32_KEY_CERT_NAME "bl32_key.crt"
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#define BL33_KEY_CERT_NAME "bl33_key.crt"
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#define BL31_CERT_NAME "bl31.crt"
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#define BL32_CERT_NAME "bl32.crt"
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#define BL33_CERT_NAME "bl33.crt"
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#define SOC_FW_KEY_CERT_NAME "soc_fw_key.crt"
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#define TOS_FW_KEY_CERT_NAME "tos_fw_key.crt"
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#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt"
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#define SOC_FW_CONTENT_CERT_NAME "soc_fw_content.crt"
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#define TOS_FW_CONTENT_CERT_NAME "tos_fw_content.crt"
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#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt"
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#endif /* TRUSTED_BOARD_BOOT */
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@ -76,36 +76,36 @@ static const io_uuid_spec_t bl33_uuid_spec = {
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};
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#if TRUSTED_BOARD_BOOT
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static const io_uuid_spec_t bl2_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2_CERT,
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static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_BOOT_FW_CERT,
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};
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static const io_uuid_spec_t trusted_key_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_KEY_CERT,
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};
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static const io_uuid_spec_t bl31_key_cert_uuid_spec = {
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.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31_KEY_CERT,
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static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = {
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.uuid = UUID_SOC_FW_KEY_CERT,
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};
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static const io_uuid_spec_t bl32_key_cert_uuid_spec = {
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.uuid = UUID_SECURE_PAYLOAD_BL32_KEY_CERT,
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static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_OS_FW_KEY_CERT,
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};
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static const io_uuid_spec_t bl33_key_cert_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33_KEY_CERT,
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static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FW_KEY_CERT,
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};
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static const io_uuid_spec_t bl31_cert_uuid_spec = {
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.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31_CERT,
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static const io_uuid_spec_t soc_fw_cert_uuid_spec = {
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.uuid = UUID_SOC_FW_CONTENT_CERT,
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};
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static const io_uuid_spec_t bl32_cert_uuid_spec = {
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.uuid = UUID_SECURE_PAYLOAD_BL32_CERT,
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static const io_uuid_spec_t tos_fw_cert_uuid_spec = {
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.uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT,
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};
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static const io_uuid_spec_t bl33_cert_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33_CERT,
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static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
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.uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT,
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};
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#endif /* TRUSTED_BOARD_BOOT */
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@ -135,36 +135,36 @@ static const io_file_spec_t sh_file_spec[] = {
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.mode = FOPEN_MODE_RB
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},
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#if TRUSTED_BOARD_BOOT
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[BL2_CERT_ID] = {
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.path = BL2_CERT_NAME,
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[TRUSTED_BOOT_FW_CERT_ID] = {
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.path = TRUSTED_BOOT_FW_CERT_NAME,
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.mode = FOPEN_MODE_RB
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},
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[TRUSTED_KEY_CERT_ID] = {
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.path = TRUSTED_KEY_CERT_NAME,
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.mode = FOPEN_MODE_RB
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},
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[BL31_KEY_CERT_ID] = {
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.path = BL31_KEY_CERT_NAME,
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[SOC_FW_KEY_CERT_ID] = {
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.path = SOC_FW_KEY_CERT_NAME,
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.mode = FOPEN_MODE_RB
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},
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[BL32_KEY_CERT_ID] = {
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.path = BL32_KEY_CERT_NAME,
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[TRUSTED_OS_FW_KEY_CERT_ID] = {
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.path = TOS_FW_KEY_CERT_NAME,
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.mode = FOPEN_MODE_RB
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},
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[BL33_KEY_CERT_ID] = {
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.path = BL33_KEY_CERT_NAME,
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[NON_TRUSTED_FW_KEY_CERT_ID] = {
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.path = NT_FW_KEY_CERT_NAME,
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.mode = FOPEN_MODE_RB
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},
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[BL31_CERT_ID] = {
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.path = BL31_CERT_NAME,
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[SOC_FW_CONTENT_CERT_ID] = {
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.path = SOC_FW_CONTENT_CERT_NAME,
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.mode = FOPEN_MODE_RB
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},
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[BL32_CERT_ID] = {
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.path = BL32_CERT_NAME,
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[TRUSTED_OS_FW_CONTENT_CERT_ID] = {
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.path = TOS_FW_CONTENT_CERT_NAME,
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.mode = FOPEN_MODE_RB
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},
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[BL33_CERT_ID] = {
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.path = BL33_CERT_NAME,
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[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
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.path = NT_FW_CONTENT_CERT_NAME,
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.mode = FOPEN_MODE_RB
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},
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#endif /* TRUSTED_BOARD_BOOT */
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@ -219,9 +219,9 @@ static const struct plat_io_policy policies[] = {
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open_fip
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},
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#if TRUSTED_BOARD_BOOT
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[BL2_CERT_ID] = {
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[TRUSTED_BOOT_FW_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl2_cert_uuid_spec,
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(uintptr_t)&tb_fw_cert_uuid_spec,
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open_fip
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},
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[TRUSTED_KEY_CERT_ID] = {
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@ -229,34 +229,34 @@ static const struct plat_io_policy policies[] = {
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(uintptr_t)&trusted_key_cert_uuid_spec,
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open_fip
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},
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[BL31_KEY_CERT_ID] = {
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[SOC_FW_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl31_key_cert_uuid_spec,
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(uintptr_t)&soc_fw_key_cert_uuid_spec,
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open_fip
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},
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[BL32_KEY_CERT_ID] = {
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[TRUSTED_OS_FW_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl32_key_cert_uuid_spec,
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(uintptr_t)&tos_fw_key_cert_uuid_spec,
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open_fip
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},
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[BL33_KEY_CERT_ID] = {
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[NON_TRUSTED_FW_KEY_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl33_key_cert_uuid_spec,
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(uintptr_t)&nt_fw_key_cert_uuid_spec,
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open_fip
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},
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[BL31_CERT_ID] = {
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[SOC_FW_CONTENT_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl31_cert_uuid_spec,
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(uintptr_t)&soc_fw_cert_uuid_spec,
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open_fip
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},
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[BL32_CERT_ID] = {
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[TRUSTED_OS_FW_CONTENT_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl32_cert_uuid_spec,
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(uintptr_t)&tos_fw_cert_uuid_spec,
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open_fip
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},
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[BL33_CERT_ID] = {
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[NON_TRUSTED_FW_CONTENT_CERT_ID] = {
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&fip_dev_handle,
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(uintptr_t)&bl33_cert_uuid_spec,
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(uintptr_t)&nt_fw_cert_uuid_spec,
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open_fip
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},
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#endif /* TRUSTED_BOARD_BOOT */
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15
plat/qemu/qemu_rotpk.S
Normal file
15
plat/qemu/qemu_rotpk.S
Normal file
@ -0,0 +1,15 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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.global qemu_rotpk_hash
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.global qemu_rotpk_hash_end
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qemu_rotpk_hash:
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/* DER header */
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.byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
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.byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
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/* SHA256 */
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.incbin ROTPK_HASH
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qemu_rotpk_hash_end:
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31
plat/qemu/qemu_trusted_boot.c
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31
plat/qemu/qemu_trusted_boot.c
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@ -0,0 +1,31 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform.h>
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extern char qemu_rotpk_hash[], qemu_rotpk_hash_end[];
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int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
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unsigned int *flags)
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{
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*key_ptr = qemu_rotpk_hash;
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*key_len = qemu_rotpk_hash_end - qemu_rotpk_hash;
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*flags = ROTPK_IS_HASH;
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return 0;
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}
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int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
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{
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*nv_ctr = 0;
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return 0;
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}
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int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
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{
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return 1;
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}
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