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Juno: Add support for TrustZone Media Protection 1 (TZMP1)
Add TZMP1 support on Juno and increase the BL2 size accordingly due to the extra data structures to describe the TZC regions and the additional code. Signed-off-by: Summer Qin <summer.qin@arm.com>
This commit is contained in:
Summer Qin
parent
23411d2c4a
commit
60a23fd8de
@ -783,6 +783,12 @@ Arm FVP platform specific build options
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HW_CONFIG blob instead of the DTS file. This option is useful to override
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the default HW_CONFIG selected by the build system.
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ARM JUNO platform specific build options
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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- ``JUNO_TZMP1`` : Boolean option to configure Juno to be used for TrustZone
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Media Protection (TZ-MP1). Default value of this flag is 0.
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Debugging options
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~~~~~~~~~~~~~~~~~
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -115,7 +115,7 @@
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# define PLAT_ARM_MAX_BL2_SIZE 0x1B000
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#endif
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#else
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# define PLAT_ARM_MAX_BL2_SIZE 0xD000
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# define PLAT_ARM_MAX_BL2_SIZE 0xE000
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#endif
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/*
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@ -4,12 +4,77 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <debug.h>
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#include <mmio.h>
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#include <nic_400.h>
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#include <plat_arm.h>
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#include <soc_css.h>
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#include "juno_def.h"
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#include "juno_def.h"
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#include "juno_tzmp1_def.h"
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#ifdef JUNO_TZMP1
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/*
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* Protect buffer for VPU/GPU/DPU memory usage with hardware protection
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* enabled. Propose 224MB video output, 96 MB video input and 32MB video
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* private.
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*
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* Ind Memory Range Caption S_ATTR NS_ATTR
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* 1 0x080000000 - 0x0E7FFFFFF ARM_NS_DRAM1 NONE RDWR | MEDIA_RW
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* 2 0x0E8000000 - 0x0F5FFFFFF JUNO_MEDIA_TZC_PROT_DRAM1 NONE MEDIA_RW | AP_WR
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* 3 0x0F6000000 - 0x0FBFFFFFF JUNO_VPU_TZC_PROT_DRAM1 RDWR VPU_PROT_RW
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* 4 0x0FC000000 - 0x0FDFFFFFF JUNO_VPU_TZC_PRIV_DRAM1 RDWR VPU_PRIV_RW
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* 5 0x0FE000000 - 0x0FEFFFFFF JUNO_AP_TZC_SHARE_DRAM1 NONE RDWR | MEDIA_RW
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* 6 0x0FF000000 - 0x0FFFFFFFF ARM_AP_TZC_DRAM1 RDWR NONE
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* 7 0x880000000 - 0x9FFFFFFFF ARM_DRAM2 NONE RDWR | MEDIA_RW
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*
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* Memory regions are neighbored to save limited TZC regions. Calculation
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* started from ARM_TZC_SHARE_DRAM1 since it is known and fixed for both
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* protected-enabled and protected-disabled settings.
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*
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* Video private buffer aheads of ARM_TZC_SHARE_DRAM1
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*/
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static const arm_tzc_regions_info_t juno_tzmp1_tzc_regions[] = {
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{ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},
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{JUNO_NS_DRAM1_PT1_BASE, JUNO_NS_DRAM1_PT1_END,
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TZC_REGION_S_NONE, JUNO_MEDIA_TZC_NS_DEV_ACCESS},
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{JUNO_MEDIA_TZC_PROT_DRAM1_BASE, JUNO_MEDIA_TZC_PROT_DRAM1_END,
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TZC_REGION_S_NONE, JUNO_MEDIA_TZC_PROT_ACCESS},
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{JUNO_VPU_TZC_PROT_DRAM1_BASE, JUNO_VPU_TZC_PROT_DRAM1_END,
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TZC_REGION_S_RDWR, JUNO_VPU_TZC_PROT_ACCESS},
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{JUNO_VPU_TZC_PRIV_DRAM1_BASE, JUNO_VPU_TZC_PRIV_DRAM1_END,
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TZC_REGION_S_RDWR, JUNO_VPU_TZC_PRIV_ACCESS},
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{JUNO_AP_TZC_SHARE_DRAM1_BASE, JUNO_AP_TZC_SHARE_DRAM1_END,
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TZC_REGION_S_NONE, JUNO_MEDIA_TZC_NS_DEV_ACCESS},
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{ARM_DRAM2_BASE, ARM_DRAM2_END,
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TZC_REGION_S_NONE, JUNO_MEDIA_TZC_NS_DEV_ACCESS},
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{},
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};
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/*******************************************************************************
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* Program dp650 to configure NSAID value for protected mode.
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******************************************************************************/
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static void init_dp650(void)
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{
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mmio_write_32(DP650_BASE + DP650_PROT_NSAID_OFFSET,
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DP650_PROT_NSAID_CONFIG);
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}
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/*******************************************************************************
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* Program v550 to configure NSAID value for protected mode.
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******************************************************************************/
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static void init_v550(void)
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{
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/*
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* bits[31:28] is for PRIVATE,
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* bits[27:24] is for OUTBUF,
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* bits[23:20] is for PROTECTED.
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*/
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mmio_write_32(V550_BASE + V550_PROTCTRL_OFFSET, V550_PROTCTRL_CONFIG);
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}
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#endif /* JUNO_TZMP1 */
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/*******************************************************************************
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* Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs
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@ -59,11 +124,23 @@ void plat_arm_security_setup(void)
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/* Initialize debug configuration */
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init_debug_cfg();
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/* Initialize the TrustZone Controller */
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#ifdef JUNO_TZMP1
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arm_tzc400_setup(juno_tzmp1_tzc_regions);
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INFO("TZC protected shared memory base address for TZMP usecase: %p\n",
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(void *)JUNO_AP_TZC_SHARE_DRAM1_BASE);
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INFO("TZC protected shared memory end address for TZMP usecase: %p\n",
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(void *)JUNO_AP_TZC_SHARE_DRAM1_END);
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#else
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arm_tzc400_setup(NULL);
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#endif
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/* Do ARM CSS internal NIC setup */
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css_init_nic400();
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/* Do ARM CSS SoC security setup */
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soc_css_security_setup();
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/* Initialize the SMMU SSD tables */
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init_mmu401();
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#ifdef JUNO_TZMP1
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init_dp650();
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init_v550();
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#endif
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}
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85
plat/arm/board/juno/juno_tzmp1_def.h
Normal file
85
plat/arm/board/juno/juno_tzmp1_def.h
Normal file
@ -0,0 +1,85 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __JUNO_TZMP1_DEF_H__
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#define __JUNO_TZMP1_DEF_H__
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#include <plat_arm.h>
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/*
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* Public memory regions for both protected and non-protected mode
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*
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* OPTEE shared memory 0xFEE00000 - 0xFEFFFFFF
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*/
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#define JUNO_AP_TZC_SHARE_DRAM1_SIZE ULL(0x02000000)
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#define JUNO_AP_TZC_SHARE_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
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JUNO_AP_TZC_SHARE_DRAM1_SIZE)
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#define JUNO_AP_TZC_SHARE_DRAM1_END (ARM_AP_TZC_DRAM1_BASE - 1)
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/* ARM_MEDIA_FEATURES for MEDIA GPU Protect Mode Test */
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#define JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE 8 /* GPU/DPU protected, VPU outbuf */
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#define JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED 7 /* VPU protected */
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#define JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE 10 /* VPU private (firmware) */
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#define JUNO_VPU_TZC_PRIV_DRAM1_SIZE ULL(0x02000000)
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#define JUNO_VPU_TZC_PRIV_DRAM1_BASE (JUNO_AP_TZC_SHARE_DRAM1_BASE - \
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JUNO_VPU_TZC_PRIV_DRAM1_SIZE)
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#define JUNO_VPU_TZC_PRIV_DRAM1_END (JUNO_AP_TZC_SHARE_DRAM1_BASE - 1)
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/* Video input protected buffer follows upper item */
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#define JUNO_VPU_TZC_PROT_DRAM1_SIZE ULL(0x06000000)
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#define JUNO_VPU_TZC_PROT_DRAM1_BASE (JUNO_VPU_TZC_PRIV_DRAM1_BASE - \
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JUNO_VPU_TZC_PROT_DRAM1_SIZE)
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#define JUNO_VPU_TZC_PROT_DRAM1_END (JUNO_VPU_TZC_PRIV_DRAM1_BASE - 1)
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/* Video, graphics and display shares same NSAID and same protected buffer */
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#define JUNO_MEDIA_TZC_PROT_DRAM1_SIZE ULL(0x0e000000)
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#define JUNO_MEDIA_TZC_PROT_DRAM1_BASE (JUNO_VPU_TZC_PROT_DRAM1_BASE - \
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JUNO_MEDIA_TZC_PROT_DRAM1_SIZE)
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#define JUNO_MEDIA_TZC_PROT_DRAM1_END (JUNO_VPU_TZC_PROT_DRAM1_BASE - 1)
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/* Rest of DRAM1 are Non-Secure public buffer */
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#define JUNO_NS_DRAM1_PT1_BASE ARM_DRAM1_BASE
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#define JUNO_NS_DRAM1_PT1_END (JUNO_MEDIA_TZC_PROT_DRAM1_BASE - 1)
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#define JUNO_NS_DRAM1_PT1_SIZE (JUNO_NS_DRAM1_PT1_END - \
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JUNO_NS_DRAM1_PT1_BASE + 1)
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/* TZC filter flags */
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#define JUNO_MEDIA_TZC_NS_DEV_ACCESS (PLAT_ARM_TZC_NS_DEV_ACCESS | \
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TZC_REGION_ACCESS_RD(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE))
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/* VPU / GPU /DPU protected access */
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#define JUNO_MEDIA_TZC_PROT_ACCESS \
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(TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_MEDIA_SECURE) | \
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TZC_REGION_ACCESS_WR(TZC400_NSAID_AP))
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#define JUNO_VPU_TZC_PROT_ACCESS \
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(TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PROTECTED))
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#define JUNO_VPU_TZC_PRIV_ACCESS \
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(TZC_REGION_ACCESS_RDWR(JUNO_TZC400_NSAID_FPGA_VIDEO_PRIVATE))
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/*******************************************************************************
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* Mali-DP650 related constants
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******************************************************************************/
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/* Base address of DP650 */
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#define DP650_BASE 0x6f200000
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/* offset to PROT_NSAID register */
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#define DP650_PROT_NSAID_OFFSET 0x10004
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/* config to PROT_NSAID register */
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#define DP650_PROT_NSAID_CONFIG 0x08008888
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/*******************************************************************************
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* Mali-V550 related constants
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******************************************************************************/
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/* Base address of V550 */
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#define V550_BASE 0x6f030000
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/* offset to PROTCTRL register */
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#define V550_PROTCTRL_OFFSET 0x0040
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/* config to PROTCTRL register */
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#define V550_PROTCTRL_CONFIG 0xa8700000
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#endif /* __JUNO_TZMP1_DEF_H__ */
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -31,6 +31,13 @@ JUNO_AARCH32_EL3_RUNTIME := 0
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$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME))
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$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME))
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# Flag to enable support for TZMP1 on JUNO
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JUNO_TZMP1 := 0
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$(eval $(call assert_boolean,JUNO_TZMP1))
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ifeq (${JUNO_TZMP1}, 1)
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$(eval $(call add_define,JUNO_TZMP1))
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endif
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ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1)
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# Include BL32 in FIP
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NEED_BL32 := yes
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