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Add ARMv8.2 ID_AA64MMFR0_EL1.PARange value

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If an implementation of ARMv8.2 includes ARMv8.2-LPA, the value 0b0110
is permitted in ID_AA64MMFR0_EL1.PARange, which means that the Physical
Address range supported is 52 bits (4 PiB). It is a reserved value
otherwise.

Change-Id: Ie0147218e9650aa09f0034a9ee03c1cca8db908a
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
Antonio Nino Diaz 2017-11-17 09:52:53 +00:00
parent e83769c07b
commit 6504b2c5b0
3 changed files with 9 additions and 2 deletions
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1
include/lib/aarch64/arch.h
View File

@ -135,6 +135,7 @@
#define PARANGE_0011 U(42)
#define PARANGE_0100 U(44)
#define PARANGE_0101 U(48)
#define PARANGE_0110 U(52)
#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
#define ID_AA64MMFR0_EL1_TGRAN4_MASK U(0xf)

5
lib/xlat_tables/aarch64/xlat_tables.c
View File

@ -60,7 +60,10 @@ static unsigned long long calc_physical_addr_size_bits(
/* Physical Address ranges supported in the AArch64 Memory Model */
static const unsigned int pa_range_bits_arr[] = {
PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
PARANGE_0101
PARANGE_0101,
#if ARM_ARCH_AT_LEAST(8, 2)
PARANGE_0110,
#endif
};
static unsigned long long get_max_supported_pa(void)

5
lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
View File

@ -48,7 +48,10 @@ unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr)
/* Physical Address ranges supported in the AArch64 Memory Model */
static const unsigned int pa_range_bits_arr[] = {
PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
PARANGE_0101
PARANGE_0101,
#if ARM_ARCH_AT_LEAST(8, 2)
PARANGE_0110,
#endif
};
unsigned long long xlat_arch_get_max_supported_pa(void)