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Manual fixes to reST documentations
Non-automated fixes to the converted documentation. Change-Id: I61f3d37c7a8d6a56a7351048060b970c5b3751e4 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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Douglas Raillard
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@ -1,6 +1,13 @@
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.. section-numbering::
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:suffix: .
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.. contents::
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ARM Trusted Firmware - version 1.3
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==================================
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New features
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------------
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@ -8,22 +8,22 @@ ARM Trusted Firmware Design
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.. contents::
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The ARM Trusted Firmware implements a subset of the Trusted Board Boot
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Requirements (TBBR) Platform Design Document (PDD) [1] for ARM reference
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Requirements (TBBR) Platform Design Document (PDD) [1]_ for ARM reference
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platforms. The TBB sequence starts when the platform is powered on and runs up
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to the stage where it hands-off control to firmware running in the normal
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world in DRAM. This is the cold boot path.
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The ARM Trusted Firmware also implements the Power State Coordination Interface
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PDD [2] as a runtime service. PSCI is the interface from normal world software
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PDD [2]_ as a runtime service. PSCI is the interface from normal world software
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to firmware implementing power management use-cases (for example, secondary CPU
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boot, hotplug and idle). Normal world software can access ARM Trusted Firmware
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runtime services via the ARM SMC (Secure Monitor Call) instruction. The SMC
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instruction must be used as mandated by the SMC Calling Convention [3].
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instruction must be used as mandated by the SMC Calling Convention [3]_.
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The ARM Trusted Firmware implements a framework for configuring and managing
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interrupts generated in either security state. The details of the interrupt
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management framework and its design can be found in ARM Trusted Firmware
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Interrupt Management Design guide [4].
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Interrupt Management Design guide [4]_.
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The ARM Trusted Firmware can be built to support either AArch64 or AArch32
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execution state.
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@ -2410,14 +2410,11 @@ kernel at boot time. These can be found in the ``fdts`` directory.
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References
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----------
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#. Trusted Board Boot Requirements CLIENT PDD (ARM DEN 0006B-5). Available
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under NDA through your ARM account representative.
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#. `Power State Coordination Interface PDD`_
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#. `SMC Calling Convention PDD`_
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#. `ARM Trusted Firmware Interrupt Management Design guide`_.
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.. [#] Trusted Board Boot Requirements CLIENT PDD (ARM DEN 0006B-5). Available
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under NDA through your ARM account representative.
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.. [#] `Power State Coordination Interface PDD`_
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.. [#] `SMC Calling Convention PDD`_
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.. [#] `ARM Trusted Firmware Interrupt Management Design guide`_.
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--------------
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@ -25,12 +25,12 @@ Generic call sequence for PSCI Library interface (AArch32)
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----------------------------------------------------------
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The generic call sequence of PSCI Library interfaces (see
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`section 4`_) during cold boot in AArch32
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`PSCI Library Interface`_) during cold boot in AArch32
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system is described below:
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#. After cold reset, the EL3 Runtime Software performs its cold boot
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initialization including the PSCI library pre-requisites mentioned in
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`section 4`_, and also the necessary platform
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`PSCI Library Interface`_, and also the necessary platform
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setup.
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#. Call ``psci_setup()`` in Monitor mode.
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@ -46,7 +46,7 @@ system is described below:
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context and exiting to non-secure world. If the EL3 Runtime Software needs
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additional configuration to be set for non-secure context, like routing
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FIQs to the secure world, the values of the registers can be modified prior
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to programming. See `section 3`_ for more
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to programming. See `PSCI CPU context management`_ for more
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details on CPU context management.
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The generic call sequence of PSCI library interfaces during warm boot in
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@ -54,7 +54,7 @@ AArch32 systems is described below:
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#. After warm reset, the EL3 Runtime Software performs the necessary warm
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boot initialization including the PSCI library pre-requisites mentioned in
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`section 4`_ (Note that the Data cache
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`PSCI Library Interface`_ (Note that the Data cache
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**must not** be enabled).
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#. Call ``psci_warmboot_entrypoint()`` in Monitor mode. This interface
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@ -75,8 +75,8 @@ on an AArch32 system is described below:
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#. If ``psci_smc_handler()`` returns, populate the return value in R0 (AArch32)/
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X0 (AArch64) and restore other registers as per `SMCCC`_.
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#. .. rubric:: PSCI CPU context management
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:name: psci-cpu-context-management
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PSCI CPU context management
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---------------------------
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PSCI library is in charge of initializing/restoring the non-secure CPU system
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registers according to `PSCI specification`_ during cold/warm boot.
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@ -120,7 +120,7 @@ registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR.
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The EL3 Runtime Software must implement accessors to get/set pointers
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to CPU context ``cpu_context_t`` data and these are described in
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`section 5.2`_.
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`CPU Context management API`_.
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PSCI Library Interface
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----------------------
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@ -208,7 +208,7 @@ must have completed. Major actions performed by this interface are:
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- Calls ``plat_setup_psci_ops()`` with warm boot entrypoint ``mailbox_ep`` as
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argument.
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- Calls ``cm_set_context_by_index()`` (see
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`section 5.2`_) for all the CPUs in the
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`CPU Context management API`_) for all the CPUs in the
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platform
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Interface : psci\_prepare\_next\_non\_secure\_ctx()
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@ -235,7 +235,7 @@ Interface : psci\_register\_spd\_pm\_hook()
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Argument : const spd_pm_ops_t *
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Return : void
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As explained in `section 5.4`_,
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As explained in `Secure payload power management callback`_,
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the EL3 Runtime Software may want to perform some bookkeeping during power
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management operations. This function is used to register the ``spd_pm_ops_t``
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(first argument) callbacks with the PSCI library which will be called
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@ -554,11 +554,7 @@ workarounds.
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.. _PSCI spec: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
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.. _SMCCC: https://silver.arm.com/download/ARM_and_AMBA_Architecture/AR570-DA-80002-r0p0-00rel0/ARM_DEN0028A_SMC_Calling_Convention.pdf
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.. _section 4: #user-content-psci-library-interface
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.. _section 3: #user-content-psci-cpu-context-management
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.. _PSCI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
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.. _section 5.2: #user-content-cpu-context-management-api
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.. _PSCI Specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
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.. _section 5.4: #user-content-secure-payload-power-management-callback
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.. _Porting Guide: porting-guide.rst
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.. _Firmware Design: ./firmware-design.rst
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@ -725,7 +725,7 @@ ignored as the linker is called directly.
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It is also possible to introduce an infinite loop to help in debugging the
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post-BL2 phase of the Trusted Firmware. This can be done by rebuilding BL1 with
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the ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the "Summary of build options"
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the ``SPIN_ON_BL1_EXIT=1`` build flag. Refer to the `Summary of build options`_
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section. In this case, the developer may take control of the target using a
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debugger when indicated by the console output. When using DS-5, the following
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commands can be used:
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@ -1721,9 +1721,7 @@ wakeup interrupt from RTC.
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.. _Linaro Release Notes: https://community.arm.com/tools/dev-platforms/b/documents/posts/linaro-release-notes-deprecated
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.. _Linaro instructions: https://community.arm.com/dev-platforms/b/documents/posts/instructions-for-using-the-linaro-software-deliverables
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.. _Development Studio 5 (DS-5): http://www.arm.com/products/tools/software-tools/ds-5/index.php
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.. _Summary of build options: #user-content-summary-of-build-options
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.. _here: ./psci-lib-integration-guide.rst
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.. _Building the Test Secure Payload: #user-content-building-the-test-secure-payload
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.. _Trusted Board Boot: trusted-board-boot.rst
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.. _Secure-EL1 Payloads and Dispatchers: firmware-design.rst#user-content-secure-el1-payloads-and-dispatchers
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.. _Firmware Update: ./firmware-update.rst
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