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AArch32: Miscellaneous fixes in the AArch32 code

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This patch makes following miscellaneous fixes:
* pl011_console.S: Fixed the bit mask used to check if the
  transmit FIFO is full or empty.
* smcc_macros.S: Added `_fsxc` suffix while updating the SPSR.
  By default the assembler assumes `_fc` suffix which does not
  update all the fields in SPSR. By adding `_fsxc` suffix all
  the fields gets updated.
* platform_helpers.S: Removed the weak definition for
  `plat_my_core_pos()` as this is a mandatory function which
  needs to be defined by all platforms.

Change-Id: I8302292533c943686fff8d7c749a07132c052a3b
Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com>
This commit is contained in:
Yatharth Kochar 2016-11-09 15:39:25 +00:00
parent c59428b150
commit 69d59e0ce9
3 changed files with 13 additions and 22 deletions
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12
drivers/arm/pl011/aarch32/pl011_console.S
View File

@ -118,15 +118,15 @@ func console_core_putc
1: 1:
/* Check if the transmit FIFO is full */ /* Check if the transmit FIFO is full */
ldr r2, [r1, #UARTFR] ldr r2, [r1, #UARTFR]
tst r2, #PL011_UARTFR_TXFF_BIT tst r2, #PL011_UARTFR_TXFF
beq 1b bne 1b
mov r2, #0xD mov r2, #0xD
str r2, [r1, #UARTDR] str r2, [r1, #UARTDR]
2: 2:
/* Check if the transmit FIFO is full */ /* Check if the transmit FIFO is full */
ldr r2, [r1, #UARTFR] ldr r2, [r1, #UARTFR]
tst r2, #PL011_UARTFR_TXFF_BIT tst r2, #PL011_UARTFR_TXFF
beq 2b bne 2b
str r0, [r1, #UARTDR] str r0, [r1, #UARTDR]
bx lr bx lr
putc_error: putc_error:
@ -149,8 +149,8 @@ func console_core_getc
1: 1:
/* Check if the receive FIFO is empty */ /* Check if the receive FIFO is empty */
ldr r1, [r0, #UARTFR] ldr r1, [r0, #UARTFR]
tst r1, #PL011_UARTFR_RXFE_BIT tst r1, #PL011_UARTFR_RXFE
beq 1b bne 1b
ldr r1, [r0, #UARTDR] ldr r1, [r0, #UARTDR]
mov r0, r1 mov r0, r1
bx lr bx lr

8
include/lib/aarch32/smcc_macros.S
View File

@ -109,7 +109,13 @@
msr spsr_und, r9 msr spsr_und, r9
msr sp_und, r10 msr sp_und, r10
msr lr_und, r11 msr lr_und, r11
msr spsr, r12 /*
* Use the `_fsxc` suffix explicitly to instruct the assembler
* to update all the 32 bits of SPSR. Else, by default, the
* assembler assumes `_fc` suffix which only modifies
* f->[31:24] and c->[7:0] bits of SPSR.
*/
msr spsr_fsxc, r12
/* Restore the rest of the general purpose registers */ /* Restore the rest of the general purpose registers */
ldm r0, {r0-r12} ldm r0, {r0-r12}

15
plat/common/aarch32/platform_helpers.S
View File

@ -31,26 +31,11 @@
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
.weak plat_my_core_pos
.weak plat_reset_handler .weak plat_reset_handler
.weak plat_disable_acp .weak plat_disable_acp
.weak platform_mem_init .weak platform_mem_init
.weak plat_panic_handler .weak plat_panic_handler
/* -----------------------------------------------------
* int plat_my_core_pos(void);
* With this function: CorePos = (ClusterId * 4) +
* CoreId
* -----------------------------------------------------
*/
func plat_my_core_pos
ldcopr r0, MPIDR
and r1, r0, #MPIDR_CPU_MASK
and r0, r0, #MPIDR_CLUSTER_MASK
add r0, r1, r0, LSR #6
bx lr
endfunc plat_my_core_pos
/* ----------------------------------------------------- /* -----------------------------------------------------
* Placeholder function which should be redefined by * Placeholder function which should be redefined by
* each platform. * each platform.