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https://github.com/CTCaer/switch-l4t-atf.git
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stm32mp1: introduce STM32MP1 discovery boards
Add the device tree files to support the 2 discovery boards: DK1 & DK2. Change-Id: I90b4797dc69bd0aab1b643a72c932ead48a03c1f Signed-off-by: Yann Gautier <yann.gautier@st.com>
This commit is contained in:
Yann Gautier
parent
0d21680c35
commit
6c1e71e1a1
121
fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
Normal file
121
fdts/stm32mp15-ddr3-1x4Gb-1066-binG.dtsi
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@ -0,0 +1,121 @@
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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/* STM32MP157C DK1/DK2 BOARD configuration
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* 1x DDR3L 4Gb, 16-bit, 533MHz.
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* Reference used NT5CC256M16DP-DI from NANYA
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*
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* DDR type / Platform DDR3/3L
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* freq 533MHz
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* width 16
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* datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G
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* DDR density 4
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* timing mode optimized
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* Scheduling/QoS options : type = 2
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* address mapping : RBC
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* Tc > + 85C : N
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*/
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#define DDR_MEM_NAME "DDR3-1066/888 bin G 1x4Gb 533MHz v1.41"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x20000000
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#define DDR_MSTR 0x00041401
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#define DDR_MRCTRL0 0x00000010
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#define DDR_MRCTRL1 0x00000000
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#define DDR_DERATEEN 0x00000000
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#define DDR_DERATEINT 0x00800000
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#define DDR_PWRCTL 0x00000000
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#define DDR_PWRTMG 0x00400010
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#define DDR_HWLPCTL 0x00000000
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#define DDR_RFSHCTL0 0x00210000
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#define DDR_RFSHCTL3 0x00000000
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#define DDR_RFSHTMG 0x0081008B
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#define DDR_CRCPARCTL0 0x00000000
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#define DDR_DRAMTMG0 0x121B2414
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#define DDR_DRAMTMG1 0x000A041C
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#define DDR_DRAMTMG2 0x0608090F
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#define DDR_DRAMTMG3 0x0050400C
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#define DDR_DRAMTMG4 0x08040608
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#define DDR_DRAMTMG5 0x06060403
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#define DDR_DRAMTMG6 0x02020002
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#define DDR_DRAMTMG7 0x00000202
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#define DDR_DRAMTMG8 0x00001005
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#define DDR_DRAMTMG14 0x000000A0
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#define DDR_ZQCTL0 0xC2000040
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#define DDR_DFITMG0 0x02060105
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#define DDR_DFITMG1 0x00000202
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#define DDR_DFILPCFG0 0x07000000
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#define DDR_DFIUPD0 0xC0400003
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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#define DDR_ADDRMAP1 0x00070707
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x1F000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x06060606
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#define DDR_ADDRMAP6 0x0F060606
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000C01
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#define DDR_SCHED1 0x00000000
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#define DDR_PERFHPR1 0x01000001
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#define DDR_PERFLPR1 0x08000200
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#define DDR_PERFWR1 0x08000400
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#define DDR_DBG0 0x00000000
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#define DDR_DBG1 0x00000000
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#define DDR_DBGCMD 0x00000000
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#define DDR_POISONCFG 0x00000000
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#define DDR_PCCFG 0x00000010
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#define DDR_PCFGR_0 0x00010000
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#define DDR_PCFGW_0 0x00000000
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#define DDR_PCFGQOS0_0 0x02100C03
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#define DDR_PCFGQOS1_0 0x00800100
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#define DDR_PCFGWQOS0_0 0x01100C03
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#define DDR_PCFGWQOS1_0 0x01000200
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#define DDR_PCFGR_1 0x00010000
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#define DDR_PCFGW_1 0x00000000
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#define DDR_PCFGQOS0_1 0x02100C03
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#define DDR_PCFGQOS1_1 0x00800040
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#define DDR_PCFGWQOS0_1 0x01100C03
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#define DDR_PCFGWQOS1_1 0x01000200
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#define DDR_PGCR 0x01442E02
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#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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#define DDR_PTR2 0x042DA068
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#define DDR_ACIOCR 0x10400812
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#define DDR_DXCCR 0x00000C40
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#define DDR_DSGCR 0xF200001F
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#define DDR_DCR 0x0000000B
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#define DDR_DTPR0 0x38D488D0
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#define DDR_DTPR1 0x098B00D8
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#define DDR_DTPR2 0x10023600
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#define DDR_MR0 0x00000840
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#define DDR_MR1 0x00000000
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#define DDR_MR2 0x00000208
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#define DDR_MR3 0x00000000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0DLLCR 0x40000000
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#define DDR_DX0DQTR 0xFFFFFFFF
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#define DDR_DX0DQSTR 0x3DB02000
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0xFFFFFFFF
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#define DDR_DX1DQSTR 0x3DB02000
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#define DDR_DX2GCR 0x0000CE81
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE81
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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#include "stm32mp15-ddr.dtsi"
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288
fdts/stm32mp157a-dk1.dts
Normal file
288
fdts/stm32mp157a-dk1.dts
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@ -0,0 +1,288 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2018-2019 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@st.com>.
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*/
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/dts-v1/;
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#include "stm32mp157c.dtsi"
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#include "stm32mp157cac-pinctrl.dtsi"
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/ {
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model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
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compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
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aliases {
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serial0 = &uart4;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};
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&clk_hse {
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st,digbypass;
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c4_pins_a>;
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i2c-scl-rising-time-ns = <185>;
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i2c-scl-falling-time-ns = <20>;
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status = "okay";
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pmic: stpmic@33 {
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compatible = "st,stpmic1";
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reg = <0x33>;
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interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
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interrupt-controller;
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#interrupt-cells = <2>;
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status = "okay";
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st,main-control-register = <0x04>;
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st,vin-control-register = <0xc0>;
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st,usb-control-register = <0x20>;
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regulators {
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compatible = "st,stpmic1-regulators";
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ldo1-supply = <&v3v3>;
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ldo3-supply = <&vdd_ddr>;
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ldo6-supply = <&v3v3>;
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vddcore: buck1 {
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regulator-name = "vddcore";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd_ddr: buck2 {
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regulator-name = "vdd_ddr";
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regulator-min-microvolt = <1350000>;
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regulator-max-microvolt = <1350000>;
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regulator-always-on;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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vdd: buck3 {
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regulator-name = "vdd";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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st,mask-reset;
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regulator-initial-mode = <0>;
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regulator-over-current-protection;
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};
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v3v3: buck4 {
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regulator-name = "v3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-over-current-protection;
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regulator-initial-mode = <0>;
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};
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v1v8_audio: ldo1 {
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regulator-name = "v1v8_audio";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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};
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v3v3_hdmi: ldo2 {
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regulator-name = "v3v3_hdmi";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vtt_ddr: ldo3 {
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regulator-name = "vtt_ddr";
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regulator-min-microvolt = <500000>;
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regulator-max-microvolt = <750000>;
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regulator-always-on;
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regulator-over-current-protection;
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};
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vdd_usb: ldo4 {
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regulator-name = "vdd_usb";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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vdda: ldo5 {
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regulator-name = "vdda";
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regulator-min-microvolt = <2900000>;
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regulator-max-microvolt = <2900000>;
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regulator-boot-on;
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};
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v1v2_hdmi: ldo6 {
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regulator-name = "v1v2_hdmi";
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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};
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vref_ddr: vref_ddr {
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regulator-name = "vref_ddr";
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regulator-always-on;
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regulator-over-current-protection;
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};
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};
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};
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};
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&iwdg2 {
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timeout-sec = <32>;
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status = "okay";
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};
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&rng1 {
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status = "okay";
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};
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&rtc {
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status = "okay";
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};
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&sdmmc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc1_b4_pins_a>;
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broken-cd;
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st,neg-edge;
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bus-width = <4>;
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vmmc-supply = <&v3v3>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_pins_a>;
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status = "okay";
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};
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/* ATF Specific */
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
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/ {
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio25 = &gpioz;
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i2c3 = &i2c4;
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};
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soc {
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stgen: stgen@5C008000 {
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compatible = "st,stm32-stgen";
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reg = <0x5C008000 0x1000>;
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status = "okay";
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};
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};
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};
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/* CLOCK init */
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&rcc {
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secure-status = "disabled";
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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CLK_PLL12_HSE
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CLK_PLL3_HSE
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CLK_PLL4_HSE
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CLK_RTC_LSE
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CLK_MCO1_DISABLED
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CLK_MCO2_DISABLED
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>;
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st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
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0 /*MCO2*/
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>;
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st,pkcs = <
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CLK_CKPER_HSE
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CLK_FMC_ACLK
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CLK_QSPI_ACLK
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CLK_ETH_DISABLED
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CLK_SDMMC12_PLL4P
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CLK_DSI_DSIPLL
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CLK_STGEN_HSE
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CLK_USBPHY_HSE
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CLK_SPI2S1_PLL3Q
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CLK_SPI2S23_PLL3Q
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CLK_SPI45_HSI
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CLK_SPI6_HSI
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CLK_I2C46_HSI
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CLK_SDMMC3_PLL4P
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CLK_USBO_USBPHY
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CLK_ADC_CKPER
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CLK_CEC_LSE
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CLK_I2C12_HSI
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CLK_I2C35_HSI
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CLK_UART1_HSI
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CLK_UART24_HSI
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CLK_UART35_HSI
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CLK_UART6_HSI
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CLK_UART78_HSI
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CLK_SPDIF_PLL4P
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CLK_FDCAN_PLL4Q
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CLK_SAI1_PLL3Q
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CLK_SAI2_PLL3Q
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CLK_SAI3_PLL3Q
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CLK_SAI4_PLL3Q
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CLK_RNG1_LSI
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CLK_RNG2_LSI
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CLK_LPTIM1_PCLK1
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CLK_LPTIM23_PCLK3
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CLK_LPTIM45_LSE
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>;
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/* VCO = 1300.0 MHz => P = 650 (CPU) */
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pll1: st,pll@0 {
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cfg = < 2 80 0 0 0 PQR(1,0,0) >;
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frac = < 0x800 >;
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};
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/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
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pll2: st,pll@1 {
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cfg = < 2 65 1 0 0 PQR(1,1,1) >;
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frac = < 0x1400 >;
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};
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/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
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pll3: st,pll@2 {
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cfg = < 1 33 1 16 36 PQR(1,1,1) >;
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frac = < 0x1a04 >;
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};
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/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
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pll4: st,pll@3 {
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cfg = < 3 98 5 7 7 PQR(1,1,1) >;
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};
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};
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16
fdts/stm32mp157c-dk2.dts
Normal file
16
fdts/stm32mp157c-dk2.dts
Normal file
@ -0,0 +1,16 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
|
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* Author: Alexandre Torgue <alexandre.torgue@st.com>.
|
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*/
|
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/dts-v1/;
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#include "stm32mp157a-dk1.dts"
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|
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/ {
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model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
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compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
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|
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};
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78
fdts/stm32mp157cac-pinctrl.dtsi
Normal file
78
fdts/stm32mp157cac-pinctrl.dtsi
Normal file
@ -0,0 +1,78 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
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/*
|
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
|
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
|
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*/
|
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|
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#include "stm32mp157-pinctrl.dtsi"
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/ {
|
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soc {
|
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pinctrl: pin-controller@50002000 {
|
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st,package = <STM32MP157CAC>;
|
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|
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gpioa: gpio@50002000 {
|
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status = "okay";
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ngpios = <16>;
|
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gpio-ranges = <&pinctrl 0 0 16>;
|
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};
|
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|
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gpiob: gpio@50003000 {
|
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status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 16 16>;
|
||||
};
|
||||
|
||||
gpioc: gpio@50004000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 32 16>;
|
||||
};
|
||||
|
||||
gpiod: gpio@50005000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 48 16>;
|
||||
};
|
||||
|
||||
gpioe: gpio@50006000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 64 16>;
|
||||
};
|
||||
|
||||
gpiof: gpio@50007000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 80 16>;
|
||||
};
|
||||
|
||||
gpiog: gpio@50008000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 96 16>;
|
||||
};
|
||||
|
||||
gpioh: gpio@50009000 {
|
||||
status = "okay";
|
||||
ngpios = <16>;
|
||||
gpio-ranges = <&pinctrl 0 112 16>;
|
||||
};
|
||||
|
||||
gpioi: gpio@5000a000 {
|
||||
status = "okay";
|
||||
ngpios = <12>;
|
||||
gpio-ranges = <&pinctrl 0 128 12>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_z: pin-controller-z@54004000 {
|
||||
st,package = <STM32MP157CAC>;
|
||||
|
||||
gpioz: gpio@54004000 {
|
||||
status = "okay";
|
||||
ngpios = <8>;
|
||||
gpio-ranges = <&pinctrl_z 0 400 8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
x
Reference in New Issue
Block a user