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https://github.com/CTCaer/switch-l4t-atf.git
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qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.
This lets the Linux kernel or any other image which expects an FDT in x0 be loaded directly as BL33 without a separate bootloader on QEMU. Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: Ia8eb4710a3d97cdd877af3b8aae36a2de7cfc654
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@ -10,6 +10,10 @@ loop to be released by normal world via PSCI.
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BL2 edits the Flattened Device Tree, FDT, generated by QEMU at run-time to
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add a node describing PSCI and also enable methods for the CPUs.
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If ``ARM_LINUX_KERNEL_AS_BL33`` is set to 1 then this FDT will be passed to BL33
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via register x0, as expected by a Linux kernel. This allows a Linux kernel image
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to be booted directly as BL33 rather than using a bootloader.
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An ARM64 defconfig v4.5 Linux kernel is known to boot, FDT doesn't need to be
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provided as it's generated by QEMU.
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@ -51,7 +51,7 @@ static void security_setup(void)
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static void update_dt(void)
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{
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int ret;
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void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE;
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void *fdt = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE;
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ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
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if (ret < 0) {
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@ -172,12 +172,12 @@ static int qemu_bl2_handle_post_image_load(unsigned int image_id)
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* OP-TEE expect to receive DTB address in x2.
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* This will be copied into x2 by dispatcher.
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*/
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bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE;
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bl_mem_params->ep_info.args.arg3 = ARM_PRELOADED_DTB_BASE;
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#else /* case AARCH32_SP_OPTEE */
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bl_mem_params->ep_info.args.arg0 =
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bl_mem_params->ep_info.args.arg1;
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bl_mem_params->ep_info.args.arg1 = 0;
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bl_mem_params->ep_info.args.arg2 = PLAT_QEMU_DT_BASE;
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bl_mem_params->ep_info.args.arg2 = ARM_PRELOADED_DTB_BASE;
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bl_mem_params->ep_info.args.arg3 = 0;
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#endif
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#endif
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@ -192,8 +192,23 @@ static int qemu_bl2_handle_post_image_load(unsigned int image_id)
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pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
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#endif
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#if ARM_LINUX_KERNEL_AS_BL33
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/*
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* According to the file ``Documentation/arm64/booting.txt`` of
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* the Linux kernel tree, Linux expects the physical address of
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* the device tree blob (DTB) in x0, while x1-x3 are reserved
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* for future use and must be 0.
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*/
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bl_mem_params->ep_info.args.arg0 =
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(u_register_t)ARM_PRELOADED_DTB_BASE;
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bl_mem_params->ep_info.args.arg1 = 0U;
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bl_mem_params->ep_info.args.arg2 = 0U;
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bl_mem_params->ep_info.args.arg3 = 0U;
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#else
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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#endif
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bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
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break;
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default:
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@ -186,5 +186,13 @@ endif
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# Process flags
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$(eval $(call add_define,BL32_RAM_LOCATION_ID))
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# Don't have the Linux kernel as a BL33 image by default
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ARM_LINUX_KERNEL_AS_BL33 := 0
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$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
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$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
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ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
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$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
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# Do not enable SVE
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ENABLE_SVE_FOR_NS := 0
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@ -97,5 +97,13 @@ PRELOADED_BL33_BASE ?= 0x10000000
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BL32_RAM_LOCATION_ID = SEC_SRAM_ID
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$(eval $(call add_define,BL32_RAM_LOCATION_ID))
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# Don't have the Linux kernel as a BL33 image by default
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ARM_LINUX_KERNEL_AS_BL33 := 0
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$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
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$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
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ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
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$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
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# Do not enable SVE
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ENABLE_SVE_FOR_NS := 0
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