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Tegra210: lift sc7exit placement restrictions

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Allow sc7exit to not be in tzdram and in non-secure or protected carveout region.

Additionally, simplify platform checks for configuration.
This commit is contained in:
CTCaer 2022-08-17 22:35:18 +00:00
parent b37f279509
commit 8817afcc78
3 changed files with 26 additions and 32 deletions
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1
plat/nvidia/tegra/include/tegra_private.h
View File

@ -68,6 +68,7 @@ typedef struct plat_params_from_bl2 {
******************************************************************************/ ******************************************************************************/
#define TEGRA_PLAT_EXTRA_FEATURES_ENABLE (0x52545845U) #define TEGRA_PLAT_EXTRA_FEATURES_ENABLE (0x52545845U)
#define TEGRA_PLAT_PMC_NON_SECURE (U(1) << U(0)) #define TEGRA_PLAT_PMC_NON_SECURE (U(1) << U(0))
#define TEGRA_PLAT_SC7_NO_BASE_RESTRICTION (U(1) << U(1))
/******************************************************************************* /*******************************************************************************
* Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs * Helper function to access l2ctlr_el1 register on Cortex-A57 CPUs

12
plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
View File

@ -461,7 +461,6 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
uint32_t cfg; uint32_t cfg;
uint32_t val, entrypoint = 0; uint32_t val, entrypoint = 0;
uint64_t offset;
/* platform parameter passed by the previous bootloader */ /* platform parameter passed by the previous bootloader */
if (plat_params->l2_ecc_parity_prot_dis != 1) { if (plat_params->l2_ecc_parity_prot_dis != 1) {
@ -517,11 +516,12 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
tegra_bpmp_resume(); tegra_bpmp_resume();
} }
if (plat_params->sc7entry_fw_base != 0U) { if (!(plat_params->flags & TEGRA_PLAT_SC7_NO_BASE_RESTRICTION) &&
/* sc7entry-fw is part of TZDRAM area */ (plat_params->sc7entry_fw_base != 0U ||
offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; plat_params->r2p_payload_base != 0U)) {
tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base, /* sc7entry-fw and r2p payload is part of TZDRAM area */
plat_params->tzdram_size + offset); tegra_memctrl_tzdram_setup(plat_params->tzdram_base - 0x100000,
plat_params->tzdram_size + 0x100000);
} }
if (!(plat_params->flags & TEGRA_PLAT_PMC_NON_SECURE) && if (!(plat_params->flags & TEGRA_PLAT_PMC_NON_SECURE) &&

45
plat/nvidia/tegra/soc/t210/plat_setup.c
View File

@ -286,38 +286,26 @@ void plat_late_platform_setup(void)
uint32_t val; uint32_t val;
/* memmap TZDRAM area containing the r2p payload firmware */ /* memmap TZDRAM area containing the r2p payload firmware */
if (plat_params->r2p_payload_base && plat_params->r2p_payload_size) { if (plat_params->r2p_payload_base) {
/* r2p payload must be _before_ BL31 base */ /* r2p payload must be _before_ BL31 base */
assert(plat_params->tzdram_base > plat_params->r2p_payload_base); assert(plat_params->tzdram_base > plat_params->r2p_payload_base);
r2p_payload_end = plat_params->r2p_payload_base + r2p_payload_end = plat_params->r2p_payload_base +
plat_params->r2p_payload_size; plat_params->r2p_payload_size;
assert(r2p_payload_end < plat_params->tzdram_base); assert(r2p_payload_end < plat_params->tzdram_base);
/* r2p payload start must be exactly 256KB behind BL31 base */
offset = plat_params->tzdram_base - plat_params->r2p_payload_base;
/* memmap r2p payload firmware code */ /* memmap r2p payload firmware code */
ret = mmap_add_dynamic_region(plat_params->r2p_payload_base, ret = mmap_add_dynamic_region(plat_params->r2p_payload_base,
plat_params->r2p_payload_base, plat_params->r2p_payload_base,
plat_params->r2p_payload_size, plat_params->r2p_payload_size,
MT_SECURE | MT_RO_DATA); MT_SECURE | MT_RO_DATA);
assert(ret == 0); assert(ret == 0);
/* clear IRAM entry OP in IRAM */ /* clear IRAM entry OP in IRAM */
*iram_entry_op = 0; *iram_entry_op = 0;
/* check if sc7entry firmware is missing */
if (!plat_params->sc7entry_fw_base || !plat_params->sc7entry_fw_size) {
/* setup secure TZDRAM area, increased by 1MB */
tegra_memctrl_tzdram_setup(plat_params->tzdram_base - 0x100000,
plat_params->tzdram_size + 0x100000);
}
} }
/* memmap TZDRAM area containing the SC7 Entry Firmware */ /* memmap TZDRAM area containing the SC7 Entry Firmware */
if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) { if (plat_params->sc7entry_fw_base) {
assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE); assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE);
/* /*
@ -335,20 +323,18 @@ void plat_late_platform_setup(void)
/* sc7entry-fw start must be exactly 1MB behind BL31 base */ /* sc7entry-fw start must be exactly 1MB behind BL31 base */
offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
assert(offset == 0x100000); if (!(plat_params->flags & TEGRA_PLAT_SC7_NO_BASE_RESTRICTION)) {
assert(offset == 0x100000);
/* secure TZDRAM area */ }
tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
plat_params->tzdram_size + offset);
/* power off BPMP processor until SC7 entry */ /* power off BPMP processor until SC7 entry */
tegra_fc_bpmp_off(); tegra_fc_bpmp_off();
/* memmap SC7 entry firmware code */ /* memmap SC7 entry firmware code */
ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base, ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base,
plat_params->sc7entry_fw_base, plat_params->sc7entry_fw_base,
plat_params->sc7entry_fw_size, plat_params->sc7entry_fw_size,
MT_SECURE | MT_RO_DATA); MT_SECURE | MT_RO_DATA);
assert(ret == 0); assert(ret == 0);
/* restrict PMC access to secure world */ /* restrict PMC access to secure world */
@ -359,6 +345,13 @@ void plat_late_platform_setup(void)
} }
} }
if (!(plat_params->flags & TEGRA_PLAT_SC7_NO_BASE_RESTRICTION) &&
(plat_params->sc7entry_fw_base || plat_params->r2p_payload_base)) {
/* secure TZDRAM area, increased by 1MB */
tegra_memctrl_tzdram_setup(plat_params->tzdram_base - 0x100000,
plat_params->tzdram_size + 0x100000);
}
if (!(plat_params->flags & TEGRA_PLAT_PMC_NON_SECURE) && if (!(plat_params->flags & TEGRA_PLAT_PMC_NON_SECURE) &&
!tegra_chipid_is_t210_b01()) { !tegra_chipid_is_t210_b01()) {
/* restrict PMC access to secure world */ /* restrict PMC access to secure world */