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https://github.com/CTCaer/switch-l4t-atf.git
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Add SPI-NOR framework
SPI-NOR framework is based on SPI-MEM framework using spi_mem_op execution interface. It implements read functions and allows NOR configuration up to quad mode. Default management is 1 data line but it can be overridden by platform. It also includes specific quad mode configuration for Spansion, Micron and Macronix memories. Change-Id: If49502b899b4a75f6ebc3190f6bde1013651197f Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
This commit is contained in:
Lionel Debieve
parent
c3e5773904
commit
a13550d0ec
387
drivers/mtd/nor/spi_nor.c
Normal file
387
drivers/mtd/nor/spi_nor.c
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@ -0,0 +1,387 @@
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stddef.h>
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <drivers/spi_nor.h>
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#include <lib/utils.h>
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#define SR_WIP BIT(0) /* Write in progress */
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#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
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#define SR_QUAD_EN_MX BIT(6) /* Macronix Quad I/O */
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#define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
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/* Defined IDs for supported memories */
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#define SPANSION_ID 0x01U
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#define MACRONIX_ID 0xC2U
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#define MICRON_ID 0x2CU
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#define BANK_SIZE 0x1000000U
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#define SPI_READY_TIMEOUT_US 40000U
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static struct nor_device nor_dev;
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#pragma weak plat_get_nor_data
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int plat_get_nor_data(struct nor_device *device)
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{
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return 0;
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}
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static int spi_nor_reg(uint8_t reg, uint8_t *buf, size_t len,
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enum spi_mem_data_dir dir)
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{
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struct spi_mem_op op;
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zeromem(&op, sizeof(struct spi_mem_op));
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op.cmd.opcode = reg;
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op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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op.data.dir = dir;
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op.data.nbytes = len;
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op.data.buf = buf;
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return spi_mem_exec_op(&op);
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}
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static inline int spi_nor_read_id(uint8_t *id)
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{
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return spi_nor_reg(SPI_NOR_OP_READ_ID, id, 1U, SPI_MEM_DATA_IN);
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}
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static inline int spi_nor_read_cr(uint8_t *cr)
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{
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return spi_nor_reg(SPI_NOR_OP_READ_CR, cr, 1U, SPI_MEM_DATA_IN);
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}
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static inline int spi_nor_read_sr(uint8_t *sr)
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{
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return spi_nor_reg(SPI_NOR_OP_READ_SR, sr, 1U, SPI_MEM_DATA_IN);
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}
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static inline int spi_nor_read_fsr(uint8_t *fsr)
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{
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return spi_nor_reg(SPI_NOR_OP_READ_FSR, fsr, 1U, SPI_MEM_DATA_IN);
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}
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static inline int spi_nor_write_en(void)
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{
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return spi_nor_reg(SPI_NOR_OP_WREN, NULL, 0U, SPI_MEM_DATA_OUT);
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}
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/*
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* Check if device is ready.
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*
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* Return 0 if ready, 1 if busy or a negative error code otherwise
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*/
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static int spi_nor_ready(void)
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{
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uint8_t sr;
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int ret;
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ret = spi_nor_read_sr(&sr);
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if (ret != 0) {
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return ret;
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}
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if ((nor_dev.flags & SPI_NOR_USE_FSR) != 0U) {
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uint8_t fsr;
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ret = spi_nor_read_fsr(&fsr);
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if (ret != 0) {
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return ret;
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}
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return (((fsr & FSR_READY) != 0U) && ((sr & SR_WIP) == 0U)) ?
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0 : 1;
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}
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return (((sr & SR_WIP) != 0U) ? 1 : 0);
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}
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static int spi_nor_wait_ready(void)
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{
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int ret;
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uint64_t timeout = timeout_init_us(SPI_READY_TIMEOUT_US);
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while (!timeout_elapsed(timeout)) {
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ret = spi_nor_ready();
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if (ret <= 0) {
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return ret;
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}
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}
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return -ETIMEDOUT;
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}
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static int spi_nor_macronix_quad_enable(void)
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{
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uint8_t sr;
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int ret;
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ret = spi_nor_read_sr(&sr);
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if (ret != 0) {
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return ret;
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}
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if ((sr & SR_QUAD_EN_MX) == 0U) {
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return 0;
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}
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ret = spi_nor_write_en();
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if (ret != 0) {
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return ret;
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}
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sr |= SR_QUAD_EN_MX;
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ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1, SPI_MEM_DATA_OUT);
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if (ret != 0) {
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return ret;
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}
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ret = spi_nor_wait_ready();
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if (ret != 0) {
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return ret;
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}
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ret = spi_nor_read_sr(&sr);
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if ((ret != 0) || ((sr & SR_QUAD_EN_MX) == 0U)) {
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return -EINVAL;
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}
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return 0;
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}
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static int spi_nor_write_sr_cr(uint8_t *sr_cr)
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{
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int ret;
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ret = spi_nor_write_en();
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if (ret != 0) {
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return ret;
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}
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ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2, SPI_MEM_DATA_OUT);
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if (ret != 0) {
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return -EINVAL;
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}
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ret = spi_nor_wait_ready();
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if (ret != 0) {
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return ret;
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}
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return 0;
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}
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static int spi_nor_quad_enable(void)
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{
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uint8_t sr_cr[2];
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int ret;
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ret = spi_nor_read_cr(&sr_cr[1]);
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if (ret != 0) {
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return ret;
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}
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if ((sr_cr[1] & CR_QUAD_EN_SPAN) != 0U) {
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return 0;
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}
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sr_cr[1] |= CR_QUAD_EN_SPAN;
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ret = spi_nor_read_sr(&sr_cr[0]);
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if (ret != 0) {
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return ret;
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}
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ret = spi_nor_write_sr_cr(sr_cr);
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if (ret != 0) {
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return ret;
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}
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ret = spi_nor_read_cr(&sr_cr[1]);
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if ((ret != 0) || ((sr_cr[1] & CR_QUAD_EN_SPAN) == 0U)) {
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return -EINVAL;
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}
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return 0;
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}
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static int spi_nor_clean_bar(void)
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{
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int ret;
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if (nor_dev.selected_bank == 0U) {
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return 0;
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}
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nor_dev.selected_bank = 0U;
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ret = spi_nor_write_en();
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if (ret != 0) {
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return ret;
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}
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return spi_nor_reg(nor_dev.bank_write_cmd, &nor_dev.selected_bank,
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1, SPI_MEM_DATA_OUT);
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}
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static int spi_nor_write_bar(uint32_t offset)
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{
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uint8_t selected_bank = offset / BANK_SIZE;
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int ret;
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if (selected_bank == nor_dev.selected_bank) {
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return 0;
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}
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ret = spi_nor_write_en();
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if (ret != 0) {
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return ret;
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}
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ret = spi_nor_reg(nor_dev.bank_write_cmd, &selected_bank,
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1, SPI_MEM_DATA_OUT);
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if (ret != 0) {
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return ret;
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}
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nor_dev.selected_bank = selected_bank;
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return 0;
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}
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static int spi_nor_read_bar(void)
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{
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uint8_t selected_bank = 0;
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int ret;
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ret = spi_nor_reg(nor_dev.bank_read_cmd, &selected_bank,
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1, SPI_MEM_DATA_IN);
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if (ret != 0) {
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return ret;
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}
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nor_dev.selected_bank = selected_bank;
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return 0;
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}
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int spi_nor_read(unsigned int offset, uintptr_t buffer, size_t length,
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size_t *length_read)
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{
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size_t remain_len;
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int ret;
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*length_read = 0;
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nor_dev.read_op.addr.val = offset;
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nor_dev.read_op.data.buf = (void *)buffer;
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VERBOSE("%s offset %i length %zu\n", __func__, offset, length);
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while (length != 0U) {
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if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) {
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ret = spi_nor_write_bar(nor_dev.read_op.addr.val);
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if (ret != 0) {
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return ret;
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}
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remain_len = (BANK_SIZE * (nor_dev.selected_bank + 1)) -
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nor_dev.read_op.addr.val;
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nor_dev.read_op.data.nbytes = MIN(length, remain_len);
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} else {
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nor_dev.read_op.data.nbytes = length;
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}
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ret = spi_mem_exec_op(&nor_dev.read_op);
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if (ret != 0) {
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spi_nor_clean_bar();
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return ret;
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}
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length -= nor_dev.read_op.data.nbytes;
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nor_dev.read_op.addr.val += nor_dev.read_op.data.nbytes;
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nor_dev.read_op.data.buf += nor_dev.read_op.data.nbytes;
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*length_read += nor_dev.read_op.data.nbytes;
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}
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if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) {
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ret = spi_nor_clean_bar();
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if (ret != 0) {
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return ret;
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}
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}
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return 0;
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}
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int spi_nor_init(unsigned long long *size, unsigned int *erase_size)
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{
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int ret = 0;
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uint8_t id;
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/* Default read command used */
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nor_dev.read_op.cmd.opcode = SPI_NOR_OP_READ;
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nor_dev.read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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nor_dev.read_op.addr.nbytes = 3U;
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nor_dev.read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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nor_dev.read_op.data.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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nor_dev.read_op.data.dir = SPI_MEM_DATA_IN;
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if (plat_get_nor_data(&nor_dev) != 0) {
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return -EINVAL;
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}
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assert(nor_dev.size != 0);
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if (nor_dev.size > BANK_SIZE) {
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nor_dev.flags |= SPI_NOR_USE_BANK;
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}
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*size = nor_dev.size;
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ret = spi_nor_read_id(&id);
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if (ret != 0) {
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return ret;
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}
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if ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U) {
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switch (id) {
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case SPANSION_ID:
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nor_dev.bank_read_cmd = SPINOR_OP_BRRD;
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nor_dev.bank_write_cmd = SPINOR_OP_BRWR;
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break;
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default:
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nor_dev.bank_read_cmd = SPINOR_OP_RDEAR;
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nor_dev.bank_write_cmd = SPINOR_OP_WREAR;
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break;
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}
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}
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if (nor_dev.read_op.data.buswidth == 4U) {
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switch (id) {
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case MACRONIX_ID:
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WARN("Enable Macronix quad support\n");
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ret = spi_nor_macronix_quad_enable();
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break;
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case MICRON_ID:
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break;
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default:
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ret = spi_nor_quad_enable();
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break;
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}
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}
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if ((ret == 0) && ((nor_dev.flags & SPI_NOR_USE_BANK) != 0U)) {
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ret = spi_nor_read_bar();
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}
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return ret;
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}
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58
include/drivers/spi_nor.h
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58
include/drivers/spi_nor.h
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@ -0,0 +1,58 @@
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DRIVERS_SPI_NOR_H
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#define DRIVERS_SPI_NOR_H
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#include <drivers/spi_mem.h>
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/* OPCODE */
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#define SPI_NOR_OP_WREN 0x06U /* Write enable */
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#define SPI_NOR_OP_WRSR 0x01U /* Write status register 1 byte */
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#define SPI_NOR_OP_READ_ID 0x9FU /* Read JEDEC ID */
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#define SPI_NOR_OP_READ_CR 0x35U /* Read configuration register */
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#define SPI_NOR_OP_READ_SR 0x05U /* Read status register */
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#define SPI_NOR_OP_READ_FSR 0x70U /* Read flag status register */
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#define SPINOR_OP_RDEAR 0xC8U /* Read Extended Address Register */
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#define SPINOR_OP_WREAR 0xC5U /* Write Extended Address Register */
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/* Used for Spansion flashes only. */
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#define SPINOR_OP_BRWR 0x17U /* Bank register write */
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#define SPINOR_OP_BRRD 0x16U /* Bank register read */
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#define SPI_NOR_OP_READ 0x03U /* Read data bytes (low frequency) */
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#define SPI_NOR_OP_READ_FAST 0x0BU /* Read data bytes (high frequency) */
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#define SPI_NOR_OP_READ_1_1_2 0x3BU /* Read data bytes (Dual Output SPI) */
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#define SPI_NOR_OP_READ_1_2_2 0xBBU /* Read data bytes (Dual I/O SPI) */
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#define SPI_NOR_OP_READ_1_1_4 0x6BU /* Read data bytes (Quad Output SPI) */
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#define SPI_NOR_OP_READ_1_4_4 0xEBU /* Read data bytes (Quad I/O SPI) */
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/* Flags for NOR specific configuration */
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#define SPI_NOR_USE_FSR BIT(0)
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#define SPI_NOR_USE_BANK BIT(1)
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struct nor_device {
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struct spi_mem_op read_op;
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uint32_t size;
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uint32_t flags;
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uint8_t selected_bank;
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uint8_t bank_write_cmd;
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uint8_t bank_read_cmd;
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};
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int spi_nor_read(unsigned int offset, uintptr_t buffer, size_t length,
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size_t *length_read);
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int spi_nor_init(unsigned long long *device_size, unsigned int *erase_size);
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/*
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* Platform can implement this to override default NOR instance configuration.
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*
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* @device: target NOR instance.
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* Return 0 on success, negative value otherwise.
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*/
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int plat_get_nor_data(struct nor_device *device);
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#endif /* DRIVERS_SPI_NOR_H */
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