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Aarch64: Add support for FEAT_PANx extensions

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This patch provides the changes listed below:
- Adds new bit fields definitions for SCTLR_EL1/2 registers
- Corrects the name of SCTLR_EL1/2.[20] bit field from
SCTLR_UWXN_BIT to SCTLR_TSCXT_BIT
- Adds FEAT_PANx bit field definitions and their possible
values for ID_AA64MMFR1_EL1 register.
- Adds setting of SCTLR_EL1.SPAN bit to preserve PSTATE.PAN
on taking an exception to EL1 in spm_sp_setup() function
(services\std_svc\spm_mm\spm_mm_setup.c)

Change-Id: If51f20e7995c649126a7728a4d0867041fdade19
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This commit is contained in:
Alexei Fedorov 2020-11-25 14:07:05 +00:00
parent 20c378920e
commit a83103c824
2 changed files with 60 additions and 3 deletions
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59
include/arch/aarch64/arch.h
View File

@ -243,6 +243,13 @@
#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
/* ID_AA64MMFR2_EL1 definitions */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
@ -286,6 +293,7 @@
#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
(UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
#define SCTLR_AARCH32_EL1_RES1 \
((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
(U(1) << 4) | (U(1) << 3))
@ -300,9 +308,12 @@
#define SCTLR_SA_BIT (ULL(1) << 3)
#define SCTLR_SA0_BIT (ULL(1) << 4)
#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
#define SCTLR_nAA_BIT (ULL(1) << 6)
#define SCTLR_ITD_BIT (ULL(1) << 7)
#define SCTLR_SED_BIT (ULL(1) << 8)
#define SCTLR_UMA_BIT (ULL(1) << 9)
#define SCTLR_EnRCTX_BIT (ULL(1) << 10)
#define SCTLR_EOS_BIT (ULL(1) << 11)
#define SCTLR_I_BIT (ULL(1) << 12)
#define SCTLR_EnDB_BIT (ULL(1) << 13)
#define SCTLR_DZE_BIT (ULL(1) << 14)
@ -310,21 +321,65 @@
#define SCTLR_NTWI_BIT (ULL(1) << 16)
#define SCTLR_NTWE_BIT (ULL(1) << 18)
#define SCTLR_WXN_BIT (ULL(1) << 19)
#define SCTLR_UWXN_BIT (ULL(1) << 20)
#define SCTLR_TSCXT_BIT (ULL(1) << 20)
#define SCTLR_IESB_BIT (ULL(1) << 21)
#define SCTLR_EIS_BIT (ULL(1) << 22)
#define SCTLR_SPAN_BIT (ULL(1) << 23)
#define SCTLR_E0E_BIT (ULL(1) << 24)
#define SCTLR_EE_BIT (ULL(1) << 25)
#define SCTLR_UCI_BIT (ULL(1) << 26)
#define SCTLR_EnDA_BIT (ULL(1) << 27)
#define SCTLR_nTLSMD_BIT (ULL(1) << 28)
#define SCTLR_LSMAOE_BIT (ULL(1) << 29)
#define SCTLR_EnIB_BIT (ULL(1) << 30)
#define SCTLR_EnIA_BIT (ULL(1) << 31)
#define SCTLR_BT0_BIT (ULL(1) << 35)
#define SCTLR_BT1_BIT (ULL(1) << 36)
#define SCTLR_BT_BIT (ULL(1) << 36)
#define SCTLR_ITFSB_BIT (ULL(1) << 37)
#define SCTLR_TCF0_SHIFT U(38)
#define SCTLR_TCF0_MASK ULL(3)
/* Tag Check Faults in EL0 have no effect on the PE */
#define SCTLR_TCF0_NO_EFFECT U(0)
/* Tag Check Faults in EL0 cause a synchronous exception */
#define SCTLR_TCF0_SYNC U(1)
/* Tag Check Faults in EL0 are asynchronously accumulated */
#define SCTLR_TCF0_ASYNC U(2)
/*
* Tag Check Faults in EL0 cause a synchronous exception on reads,
* and are asynchronously accumulated on writes
*/
#define SCTLR_TCF0_SYNCR_ASYNCW U(3)
#define SCTLR_TCF_SHIFT U(40)
#define SCTLR_TCF_MASK ULL(3)
/* Tag Check Faults in EL1 have no effect on the PE */
#define SCTLR_TCF_NO_EFFECT U(0)
/* Tag Check Faults in EL1 cause a synchronous exception */
#define SCTLR_TCF_SYNC U(1)
/* Tag Check Faults in EL1 are asynchronously accumulated */
#define SCTLR_TCF_ASYNC U(2)
/*
* Tag Check Faults in EL1 cause a synchronous exception on reads,
* and are asynchronously accumulated on writes
*/
#define SCTLR_TCF_SYNCR_ASYNCW U(3)
#define SCTLR_ATA0_BIT (ULL(1) << 42)
#define SCTLR_ATA_BIT (ULL(1) << 43)
#define SCTLR_DSSBS_BIT (ULL(1) << 44)
#define SCTLR_TWEDEn_BIT (ULL(1) << 45)
#define SCTLR_TWEDEL_SHIFT U(46)
#define SCTLR_TWEDEL_MASK ULL(0xf)
#define SCTLR_EnASR_BIT (ULL(1) << 54)
#define SCTLR_EnAS0_BIT (ULL(1) << 55)
#define SCTLR_EnALS_BIT (ULL(1) << 56)
#define SCTLR_EPAN_BIT (ULL(1) << 57)
#define SCTLR_RESET_VAL SCTLR_EL3_RES1
/* CPACR_El1 definitions */
/* CPACR_EL1 definitions */
#define CPACR_EL1_FPEN(x) ((x) << 20)
#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
#define CPACR_EL1_FP_TRAP_ALL UL(0x2)

4
services/std_svc/spm_mm/spm_mm_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -142,6 +142,8 @@ void spm_sp_setup(sp_context_t *sp_ctx)
SCTLR_DZE_BIT |
/* Enable SP Alignment check for EL0 */
SCTLR_SA0_BIT |
/* Don't change PSTATE.PAN on taking an exception to EL1 */
SCTLR_SPAN_BIT |
/* Allow cacheable data and instr. accesses to normal memory. */
SCTLR_C_BIT | SCTLR_I_BIT |
/* Enable MMU. */