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intel: agilex: Fix psci power domain off

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Disable gic cpu interface for powered down cpu. This patch also removes
core reset during power off as core reset will be done during power on

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2ca96d876b6e71e56d24a9a7e184b6d6226b8673
This commit is contained in:
Hadi Asyrafi 2019-09-12 15:14:01 +08:00
parent 5dbdf8e4ea
commit afac9681ff
1 changed files with 2 additions and 8 deletions
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10
plat/intel/soc/agilex/socfpga_psci.c
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@ -61,18 +61,12 @@ int socfpga_pwr_domain_on(u_register_t mpidr)
******************************************************************************/
void socfpga_pwr_domain_off(const psci_power_state_t *target_state)
{
unsigned int cpu_id = plat_my_core_pos();
for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
/* TODO: Prevent interrupts from spuriously waking up this cpu */
/* gicv2_cpuif_disable(); */
/* assert core reset */
mmio_setbits_32(AGX_RSTMGR_OFST + AGX_RSTMGR_MPUMODRST_OFST,
1 << cpu_id);
/* Prevent interrupts from spuriously waking up this cpu */
gicv2_cpuif_disable();
}
/*******************************************************************************