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drivers: Add Cadence UART driver
Add a driver for the Cadence UART which is found in Xilinx Zynq SOCs. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
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Soren Brinkmann
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127
drivers/cadence/uart/cdns_console.S
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127
drivers/cadence/uart/cdns_console.S
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cadence/cdns_uart.h>
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.globl console_core_init
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.globl console_core_putc
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.globl console_core_getc
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/* -----------------------------------------------
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* int console_core_init(unsigned long base_addr,
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* unsigned int uart_clk, unsigned int baud_rate)
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* Function to initialize the console without a
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* C Runtime to print debug information. This
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* function will be accessed by console_init and
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* crash reporting.
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* We assume that the bootloader already set up
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* the HW (baud, ...) and only enable the trans-
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* mitter and receiver here.
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* In: x0 - console base address
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* w1 - Uart clock in Hz
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* w2 - Baud rate
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* Out: return 1 on success else 0 on error
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* Clobber list : x1, x2, x3
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* -----------------------------------------------
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*/
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func console_core_init
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/* Check the input base address */
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cbz x0, core_init_fail
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/* Check baud rate and uart clock for sanity */
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cbz w1, core_init_fail
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cbz w2, core_init_fail
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/* RX/TX enabled & reset */
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mov w3, #(R_UART_CR_TX_EN | R_UART_CR_RX_EN | R_UART_CR_TXRST | R_UART_CR_RXRST)
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str w3, [x0, #R_UART_CR]
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mov w0, #1
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ret
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core_init_fail:
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mov w0, wzr
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ret
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endfunc console_core_init
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/* --------------------------------------------------------
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* int console_core_putc(int c, unsigned long base_addr)
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* Function to output a character over the console. It
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* returns the character printed on success or -1 on error.
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* In : w0 - character to be printed
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* x1 - console base address
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* Out : return -1 on error else return character.
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* Clobber list : x2
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* --------------------------------------------------------
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*/
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func console_core_putc
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/* Check the input parameter */
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cbz x1, putc_error
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/* Prepend '\r' to '\n' */
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cmp w0, #0xA
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b.ne 2f
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1:
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/* Check if the transmit FIFO is full */
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ldr w2, [x1, #R_UART_SR]
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tbnz w2, #UART_SR_INTR_TFUL_BIT, 1b
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mov w2, #0xD
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str w2, [x1, #R_UART_TX]
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2:
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/* Check if the transmit FIFO is full */
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ldr w2, [x1, #R_UART_SR]
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tbnz w2, #UART_SR_INTR_TFUL_BIT, 2b
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str w0, [x1, #R_UART_TX]
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ret
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putc_error:
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mov w0, #-1
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ret
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endfunc console_core_putc
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/* ---------------------------------------------
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* int console_core_getc(unsigned long base_addr)
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* Function to get a character from the console.
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* It returns the character grabbed on success
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* or -1 on error.
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* In : x0 - console base address
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func console_core_getc
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cbz x0, getc_error
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1:
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/* Check if the receive FIFO is empty */
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ldr w1, [x0, #R_UART_SR]
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tbnz w1, #UART_SR_INTR_REMPTY_BIT, 1b
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ldr w1, [x0, #R_UART_RX]
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mov w0, w1
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ret
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getc_error:
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mov w0, #-1
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ret
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endfunc console_core_getc
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50
include/drivers/cadence/cdns_uart.h
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50
include/drivers/cadence/cdns_uart.h
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@ -0,0 +1,50 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CADENCE_UART_H__
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#define __CADENCE_UART_H__
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/* This is very minimalistic and will only work in QEMU. */
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/* CADENCE Registers */
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#define R_UART_CR 0
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#define R_UART_CR_RXRST (1 << 0) /* RX logic reset */
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#define R_UART_CR_TXRST (1 << 1) /* TX logic reset */
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#define R_UART_CR_RX_EN (1 << 2) /* RX enabled */
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#define R_UART_CR_TX_EN (1 << 4) /* TX enabled */
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#define R_UART_SR 0x2C
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#define UART_SR_INTR_REMPTY_BIT 1
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#define UART_SR_INTR_TFUL_BIT 4
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#define R_UART_TX 0x30
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#define R_UART_RX 0x30
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#endif
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