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Merge "TF-A GIC driver: Add barrier before eoi" into integration

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This commit is contained in:
Madhukar Pappireddy 2020-06-22 19:57:52 +00:00 committed by TrustedFirmware Code Review
commit b667b3696b
2 changed files with 33 additions and 0 deletions
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9
drivers/arm/gic/v2/gicv2_main.c
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@ -247,6 +247,15 @@ void gicv2_end_of_interrupt(unsigned int id)
assert(driver_data != NULL);
assert(driver_data->gicc_base != 0U);
/*
* Ensure the write to peripheral registers are *complete* before the write
* to GIC_EOIR.
*
* Note: The completion gurantee depends on various factors of system design
* and the barrier is the best core can do by which execution of further
* instructions waits till the barrier is alive.
*/
dsbishst();
gicc_write_EOIR(driver_data->gicc_base, id);
}

24
include/drivers/arm/gicv3.h
View File

@ -332,6 +332,18 @@ static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void)
static inline void gicv3_end_of_interrupt_sel1(unsigned int id)
{
/*
* Interrupt request deassertion from peripheral to GIC happens
* by clearing interrupt condition by a write to the peripheral
* register. It is desired that the write transfer is complete
* before the core tries to change GIC state from 'AP/Active' to
* a new state on seeing 'EOI write'.
* Since ICC interface writes are not ordered against Device
* memory writes, a barrier is required to ensure the ordering.
* The dsb will also ensure *completion* of previous writes with
* DEVICE nGnRnE attribute.
*/
dsbishst();
write_icc_eoir1_el1(id);
}
@ -345,6 +357,18 @@ static inline uint32_t gicv3_acknowledge_interrupt(void)
static inline void gicv3_end_of_interrupt(unsigned int id)
{
/*
* Interrupt request deassertion from peripheral to GIC happens
* by clearing interrupt condition by a write to the peripheral
* register. It is desired that the write transfer is complete
* before the core tries to change GIC state from 'AP/Active' to
* a new state on seeing 'EOI write'.
* Since ICC interface writes are not ordered against Device
* memory writes, a barrier is required to ensure the ordering.
* The dsb will also ensure *completion* of previous writes with
* DEVICE nGnRnE attribute.
*/
dsbishst();
return write_icc_eoir0_el1(id);
}