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rcar_gen3: drivers: ddr: Update DDR setting for H3, M3, M3N
[IPL/DDR] - Update H3, M3, M3N DDR setting rev.0.38. Signed-off-by: Chiaki Fujii <chiaki.fujii.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> # upstream update Change-Id: I49cf8f778b849a6ee97bc9f6948c45b07dc467b1
This commit is contained in:
Chiaki Fujii
Marek Vasut
parent
2701a05836
commit
ba63b5c93e
@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2019, Renesas Electronics Corporation.
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* Copyright (c) 2015-2020, Renesas Electronics Corporation.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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@ -2383,37 +2383,6 @@ static void dbsc_regset_post(void)
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mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff));
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mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
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#ifdef DDR_BACKUPMODE
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if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
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#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0,1 only) */
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DEBUG(" DEBUG_MESS : DDR_BACKUPMODE_HALF ", 1);
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send_dbcmd(0x08040001);
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wait_dbcmd();
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send_dbcmd(0x0A040001);
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wait_dbcmd();
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send_dbcmd(0x04040010);
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wait_dbcmd();
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if (prr_product == PRR_PRODUCT_H3) {
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send_dbcmd(0x08140001);
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wait_dbcmd();
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send_dbcmd(0x0A140001);
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wait_dbcmd();
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send_dbcmd(0x04140010);
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wait_dbcmd();
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}
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#else /* DDR_BACKUPMODE_HALF //for All channels */
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send_dbcmd(0x08840001);
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wait_dbcmd();
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send_dbcmd(0x0A840001);
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wait_dbcmd();
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send_dbcmd(0x04840010);
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wait_dbcmd();
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#endif /* DDR_BACKUPMODE_HALF */
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}
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#endif /* DDR_BACKUPMODE */
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#if RCAR_REWT_TRAINING != 0
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/* Periodic-WriteDQ Training seeting */
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if (((prr_product == PRR_PRODUCT_H3) &&
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@ -2422,12 +2391,7 @@ static void dbsc_regset_post(void)
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(prr_cut == PRR_PRODUCT_10))) {
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/* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
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} else {
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/*
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* H3 Ver.2.0 or later/M3-W Ver.1.1 or
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* later/M3-N/V3H -> Periodic-WriteDQ Training seeting
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*/
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/* Periodic WriteDQ Training seeting */
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/* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
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mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000);
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ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04);
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@ -2440,7 +2404,6 @@ static void dbsc_regset_post(void)
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_reg_PI_WDQLVL_CS_MAP));
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ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f);
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ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00);
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ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100);
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ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01);
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ddr_setval_ach(_reg_PI_TREF_F0, 0x0000);
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ddr_setval_ach(_reg_PI_TREF_F1, 0x0000);
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@ -2458,8 +2421,10 @@ static void dbsc_regset_post(void)
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mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011);
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}
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#endif /* RCAR_REWT_TRAINING */
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/* periodic dram zqcal and phy ctrl update enable */
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/* periodic dram zqcal enable */
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mmio_write_32(DBSC_DBCALCNF, 0x01000010);
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/* periodic phy ctrl update enable */
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if (((prr_product == PRR_PRODUCT_H3) &&
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(prr_cut <= PRR_PRODUCT_11)) ||
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((prr_product == PRR_PRODUCT_M3) &&
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@ -2477,7 +2442,36 @@ static void dbsc_regset_post(void)
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#endif /* RCAR_DRAM_SPLIT == 2 */
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}
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#ifdef DDR_BACKUPMODE
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/* SRX */
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if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
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#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */
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NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n");
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send_dbcmd(0x0A040001);
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if (Prr_Product == PRR_PRODUCT_H3)
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send_dbcmd(0x0A140001);
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#else /* DDR_BACKUPMODE_HALF */ /* for All channels */
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send_dbcmd(0x0A840001);
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#endif /* DDR_BACKUPMODE_HALF */
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}
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#endif /* DDR_BACKUPMODE */
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/* set Auto Refresh */
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mmio_write_32(DBSC_DBRFEN, 0x00000001);
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#if RCAR_REWT_TRAINING != 0
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/* Periodic WriteDQ Traning */
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if (((prr_product == PRR_PRODUCT_H3) &&
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(prr_cut <= PRR_PRODUCT_11)) ||
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((prr_product == PRR_PRODUCT_M3) &&
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(prr_cut == PRR_PRODUCT_10))) {
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/* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
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} else {
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/* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
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ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100);
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}
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#endif /* RCAR_REWT_TRAINING */
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/* dram access enable */
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mmio_write_32(DBSC_DBACEN, 0x00000001);
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@ -3026,6 +3020,9 @@ static uint32_t init_ddr(void)
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return INITDRAM_ERR_O;
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MSG_LF(__func__ ":5\n");
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/* Dummy PDE */
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send_dbcmd(0x08840000);
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/* PDX */
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send_dbcmd(0x08840001);
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2019, Renesas Electronics Corporation.
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* Copyright (c) 2015-2020, Renesas Electronics Corporation.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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@ -1571,8 +1571,13 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
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{
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uint32_t md;
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md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5;
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md = (md | (md >> 1)) & 0x3;
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if (prr_product == PRR_PRODUCT_V3H) {
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md = (mmio_read_32(RST_MODEMR) >> 19) & 0x1;
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md = (md | (md << 1)) & 0x3; /* 0 or 3 */
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} else {
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md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5;
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md = (md | (md >> 1)) & 0x3;
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}
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switch (md) {
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case 0x0:
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*mbps = 3200;
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@ -1,11 +1,11 @@
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/*
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* Copyright (c) 2015-2019, Renesas Electronics Corporation.
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* Copyright (c) 2015-2020, Renesas Electronics Corporation.
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define RCAR_DDR_VERSION "rev.0.37"
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#define RCAR_DDR_VERSION "rev.0.38"
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#define DRAM_CH_CNT 0x04
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#define SLICE_CNT 0x04
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#define CS_CNT 0x02
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@ -22,7 +22,7 @@
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/* for ddr deisity setting */
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#define DBMEMCONF_REG(d3, row, bank, col, dw) \
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((d3) << 30 | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
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(((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
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#define DBMEMCONF_REGD(density) \
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(DBMEMCONF_REG((density) % 2, ((density) + 1) / \
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