diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 07fadd154..8e6044551 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -404,6 +404,7 @@ func cortex_a57_reset_func
 #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
 	adr	x0, wa_cve_2017_5715_mmu_vbar
 	msr	vbar_el3, x0
+	/* isb will be performed before returning from this function */
 #endif
 
 #if WORKAROUND_CVE_2018_3639
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index bb9381d17..38b76b940 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -137,6 +137,7 @@ func cortex_a72_reset_func
 	cpu_check_csv2	x0, 1f
 	adr	x0, wa_cve_2017_5715_mmu_vbar
 	msr	vbar_el3, x0
+	/* isb will be performed before returning from this function */
 1:
 #endif
 
diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index d595f128f..b79656135 100644
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S
@@ -40,6 +40,7 @@ func cortex_a73_reset_func
 	cpu_check_csv2	x0, 1f
 	adr	x0, wa_cve_2017_5715_bpiall_vbar
 	msr	vbar_el3, x0
+	/* isb will be performed before returning from this function */
 1:
 #endif
 
diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S
index 20ec32ce2..73f566f4b 100644
--- a/lib/cpus/aarch64/cortex_a75.S
+++ b/lib/cpus/aarch64/cortex_a75.S
@@ -15,6 +15,7 @@ func cortex_a75_reset_func
 	cpu_check_csv2	x0, 1f
 	adr	x0, wa_cve_2017_5715_bpiall_vbar
 	msr	vbar_el3, x0
+	isb
 1:
 #endif