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Merge pull request #835 from rockchip-linux/rk3399-atf-cleanup-20170210

Browse Source 
RK3399 ARM TF clean up 20170210
This commit is contained in:
davidcunado-arm 2017-02-27 15:25:45 +00:00 committed by GitHub
commit d6845d3dc3
37 changed files with 2567 additions and 2433 deletions
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1
plat/rockchip/common/include/plat_private.h
View File

@ -44,6 +44,7 @@
extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end;
extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end;
extern uint32_t __sram_incbin_start, __sram_incbin_end;
/******************************************************************************
* For rockchip socs pm ops

6
plat/rockchip/common/pmusram/pmu_sram.c
View File

@ -62,6 +62,12 @@ void rockchip_plat_sram_mmu_el3(void)
mmap_add_region((unsigned long)&__bl31_sram_data_start,
(unsigned long)&__bl31_sram_data_start,
sram_size, MT_MEMORY | MT_RW | MT_SECURE);
/* sram.incbin size */
sram_size = (char *)&__sram_incbin_end - (char *)&__sram_incbin_start;
mmap_add_region((unsigned long)&__sram_incbin_start,
(unsigned long)&__sram_incbin_start,
sram_size, MT_NON_CACHEABLE | MT_RW | MT_SECURE);
#else
/* TODO: Support other SoCs, Just support RK3399 now */
return;

364
plat/rockchip/rk3399/drivers/dram/dcf_code.inc
View File

@ -1,364 +0,0 @@
0x0 ,
0x4f8c120c ,
0x0 ,
0x4f8c1210 ,
0x100000 ,
0x1f310019 ,
0x0 ,
0xb0000001 ,
0x58 ,
0xd0000000 ,
0x1300 ,
0x1f760329 ,
0x0 ,
0xb0000001 ,
0x40 ,
0xd0000000 ,
0xc ,
0x1f760371 ,
0x0 ,
0xb0000001 ,
0x28 ,
0xd0000000 ,
0x400000 ,
0x1f900009 ,
0x0 ,
0xb0000001 ,
0x10 ,
0xd0000000 ,
0x1 ,
0x4f8c120c ,
0x100000 ,
0x1f310019 ,
0x0 ,
0xb0000001 ,
0x58 ,
0xd0000000 ,
0x2c00 ,
0x1f760329 ,
0x0 ,
0xb0000001 ,
0x40 ,
0xd0000000 ,
0xc0 ,
0x1f760371 ,
0x0 ,
0xb0000001 ,
0x28 ,
0xd0000000 ,
0x400000 ,
0x1f8f0009 ,
0x0 ,
0xb0000001 ,
0x10 ,
0xd0000000 ,
0x1 ,
0x4f8c1210 ,
0x0 ,
0x4f8c1220 ,
0x0 ,
0x4f8c121c ,
0x0 ,
0xaf8c120d ,
0x108 ,
0xd0000000 ,
0x2000 ,
0x1f900009 ,
0x0 ,
0xa0000001 ,
0x30 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x0 ,
0x4f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
0xa0000001 ,
0xb0 ,
0xd0000000 ,
0x8000 ,
0x1f900009 ,
0x0 ,
0xa0000001 ,
0x30 ,
0xd0000000 ,
0x1 ,
0x4f8c1220 ,
0x1 ,
0x4f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
0xa0000001 ,
0x70 ,
0xd0000000 ,
0x4000 ,
0x1f900009 ,
0x0 ,
0xa0000001 ,
0x30 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x1 ,
0x4f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
0xa0000001 ,
0x30 ,
0xd0000000 ,
0x1000 ,
0x1f900009 ,
0x0 ,
0xa0000001 ,
0x18 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x1 ,
0x4f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
0xa0000001 ,
0x100 ,
0xd0000000 ,
0x0 ,
0xaf8c1211 ,
0xf0 ,
0xd0000000 ,
0x2000 ,
0x1f8f0009 ,
0x0 ,
0xa0000001 ,
0x30 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x0 ,
0x4f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
0xa0000001 ,
0xb0 ,
0xd0000000 ,
0x8000 ,
0x1f8f0009 ,
0x0 ,
0xa0000001 ,
0x30 ,
0xd0000000 ,
0x1 ,
0x4f8c1220 ,
0x1 ,
0x4f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
0xa0000001 ,
0x70 ,
0xd0000000 ,
0x4000 ,
0x1f8f0009 ,
0x0 ,
0xa0000001 ,
0x30 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x1 ,
0x4f8c121c ,
0x0 ,
0x10000001 ,
0x0 ,
0xa0000001 ,
0x30 ,
0xd0000000 ,
0x1000 ,
0x1f8f0009 ,
0x0 ,
0xa0000001 ,
0x18 ,
0xd0000000 ,
0x0 ,
0x4f8c1220 ,
0x1 ,
0x4f8c121c ,
0x0 ,
0xaf8c120d ,
0x40 ,
0xd0000000 ,
0x80008000 ,
0x7f900284 ,
0x1 ,
0x0 ,
0x8000 ,
0x1f90028d ,
0x0 ,
0x60000001 ,
0x0 ,
0x10000001 ,
0x0 ,
0xa0000001 ,
0x38 ,
0xd0000000 ,
0x0 ,
0xaf8c1211 ,
0x28 ,
0xd0000000 ,
0x80008000 ,
0x7f8f0284 ,
0x1 ,
0x0 ,
0x8000 ,
0x1f8f028d ,
0x0 ,
0x60000001 ,
0xffffffff ,
0x4f77e200 ,
0xffffffff ,
0x4f77e204 ,
0xffffffff ,
0x4f77e208 ,
0xffffffff ,
0x4f77e20c ,
0x70007000 ,
0x4f77e210 ,
0x3fffffff ,
0x7f750130 ,
0x0 ,
0x2f310061 ,
0xc0000 ,
0x20000001 ,
0x0 ,
0x4f310061 ,
0xc0000 ,
0x1f310065 ,
0xc0000 ,
0xb0000001 ,
0x10 ,
0xc0000000 ,
0x0 ,
0xaf8c121d ,
0x48 ,
0xd0000000 ,
0x0 ,
0xaf8c120d ,
0x18 ,
0xd0000000 ,
0x80000000 ,
0x2f90000d ,
0x0 ,
0x4f90000d ,
0x0 ,
0xaf8c1211 ,
0x18 ,
0xd0000000 ,
0x80000000 ,
0x2f90000d ,
0x0 ,
0x4f8f000d ,
0x0 ,
0x2f8c101d ,
0x350005 ,
0x20000001 ,
0x0 ,
0x4f620001 ,
0x1 ,
0x0 ,
0x4 ,
0x1f620011 ,
0x0 ,
0x60000001 ,
0x3000000 ,
0x7f76004c ,
0x18 ,
0x0 ,
0x10001 ,
0x7f76004c ,
0x0 ,
0x2f8c1005 ,
0x0 ,
0x4f760041 ,
0x0 ,
0x2f8c1009 ,
0x0 ,
0x4f760045 ,
0x10000 ,
0x7f76004c ,
0x18 ,
0x0 ,
0x1 ,
0x0 ,
0x80000000 ,
0x1f760049 ,
0x0 ,
0x60000001 ,
0x3000100 ,
0x7f76004c ,
0x3e8 ,
0x0 ,
0x20002 ,
0x4f620000 ,
0x1 ,
0x0 ,
0x1 ,
0x1f620011 ,
0x0 ,
0x60000001 ,
0x0 ,
0xaf8c121d ,
0x48 ,
0xd0000000 ,
0x0 ,
0xaf8c120d ,
0x18 ,
0xd0000000 ,
0x7fffffff ,
0x1f90000d ,
0x0 ,
0x4f90000d ,
0x0 ,
0xaf8c1211 ,
0x18 ,
0xd0000000 ,
0x7fffffff ,
0x1f90000d ,
0x0 ,
0x4f8f000d ,
0xfff3ffff ,
0x1f310061 ,
0x0 ,
0x7f310061 ,
0xc0000 ,
0x1f310065 ,
0x0 ,
0xb0000001 ,
0x10 ,
0xc0000000 ,
0x0 ,
0x7f750130 ,
0x1 ,
0x0 ,
0x1 ,
0x0 ,
0x1 ,
0x0 ,
0x1 ,
0x0 ,
0x1 ,
0x0 ,
0x1 ,
0x0 ,
0x1 ,
0x0 ,
0x1 ,
0x0 ,
0x1 ,
0x0 ,
0x0 ,
0xe0000000 ,

954
plat/rockchip/rk3399/drivers/dram/dfs.c
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File diff suppressed because it is too large Load Diff

52
plat/rockchip/rk3399/drivers/dram/dfs.h
View File

@ -48,65 +48,25 @@ struct rk3399_sdram_default_config {
unsigned char zqcsi;
};
struct ddr_dts_config_timing {
unsigned int ddr3_speed_bin;
unsigned int pd_idle;
unsigned int sr_idle;
unsigned int sr_mc_gate_idle;
unsigned int srpd_lite_idle;
unsigned int standby_idle;
unsigned int auto_pd_dis_freq;
unsigned int ddr3_dll_dis_freq;
unsigned int phy_dll_dis_freq;
unsigned int ddr3_odt_dis_freq;
unsigned int ddr3_drv;
unsigned int ddr3_odt;
unsigned int phy_ddr3_ca_drv;
unsigned int phy_ddr3_dq_drv;
unsigned int phy_ddr3_odt;
unsigned int lpddr3_odt_dis_freq;
unsigned int lpddr3_drv;
unsigned int lpddr3_odt;
unsigned int phy_lpddr3_ca_drv;
unsigned int phy_lpddr3_dq_drv;
unsigned int phy_lpddr3_odt;
unsigned int lpddr4_odt_dis_freq;
unsigned int lpddr4_drv;
unsigned int lpddr4_dq_odt;
unsigned int lpddr4_ca_odt;
unsigned int phy_lpddr4_ca_drv;
unsigned int phy_lpddr4_ck_cs_drv;
unsigned int phy_lpddr4_dq_drv;
unsigned int phy_lpddr4_odt;
uint32_t available;
};
struct drv_odt_lp_config {
uint32_t ddr3_speed_bin;
uint32_t pd_idle;
uint32_t sr_idle;
uint32_t sr_mc_gate_idle;
uint32_t srpd_lite_idle;
uint32_t standby_idle;
uint32_t ddr3_dll_dis_freq;/* for ddr3 only */
uint32_t phy_dll_dis_freq;
uint32_t odt_dis_freq;
uint32_t odt_en;
uint32_t dram_side_drv;
uint32_t dram_side_dq_odt;
uint32_t dram_side_ca_odt;
uint32_t phy_side_ca_drv;
uint32_t phy_side_ck_cs_drv;
uint32_t phy_side_dq_drv;
uint32_t phy_side_odt;
};
void ddr_dfs_init(void);
uint32_t ddr_set_rate(uint32_t hz);
uint32_t ddr_round_rate(uint32_t hz);
uint32_t ddr_get_rate(void);
void clr_dcf_irq(void);
uint32_t dts_timing_receive(uint32_t timing, uint32_t index);
uint32_t dram_set_odt_pd(uint32_t arg0, uint32_t arg1, uint32_t arg2);
void dram_dfs_init(void);
void ddr_prepare_for_sys_suspend(void);
void ddr_prepare_for_sys_resume(void);
#endif

1
plat/rockchip/rk3399/drivers/dram/dram.c
View File

@ -30,6 +30,7 @@
#include <dram.h>
#include <plat_private.h>
#include <secure.h>
#include <soc.h>
#include <rk3399_def.h>

105
plat/rockchip/rk3399/drivers/dram/dram.h
View File

@ -30,111 +30,11 @@
#ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__
#define __SOC_ROCKCHIP_RK3399_DRAM_H__
#include <dram_regs.h>
#include <plat_private.h>
#include <stdint.h>
#define CTL_BASE(ch) (0xffa80000 + (ch) * 0x8000)
#define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4)
#define PI_OFFSET 0x800
#define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET)
#define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4)
#define PHY_OFFSET 0x2000
#define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET)
#define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4)
#define MSCH_BASE(ch) (0xffa84000 + (ch) * 0x8000)
#define MSCH_ID_COREID 0x0
#define MSCH_ID_REVISIONID 0x4
#define MSCH_DEVICECONF 0x8
#define MSCH_DEVICESIZE 0xc
#define MSCH_DDRTIMINGA0 0x10
#define MSCH_DDRTIMINGB0 0x14
#define MSCH_DDRTIMINGC0 0x18
#define MSCH_DEVTODEV0 0x1c
#define MSCH_DDRMODE 0x110
#define MSCH_AGINGX0 0x1000
#define CIC_CTRL0 0x0
#define CIC_CTRL1 0x4
#define CIC_IDLE_TH 0x8
#define CIC_CG_WAIT_TH 0xc
#define CIC_STATUS0 0x10
#define CIC_STATUS1 0x14
#define CIC_CTRL2 0x18
#define CIC_CTRL3 0x1c
#define CIC_CTRL4 0x20
/* DENALI_CTL_00 */
#define START 1
/* DENALI_CTL_68 */
#define PWRUP_SREFRESH_EXIT (1 << 16)
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
#define PHY_DRV_ODT_Hi_Z 0x0
#define PHY_DRV_ODT_240 0x1
#define PHY_DRV_ODT_120 0x8
#define PHY_DRV_ODT_80 0x9
#define PHY_DRV_ODT_60 0xc
#define PHY_DRV_ODT_48 0xd
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
/*
* sys_reg bitfield struct
* [31] row_3_4_ch1
* [30] row_3_4_ch0
* [29:28] chinfo
* [27] rank_ch1
* [26:25] col_ch1
* [24] bk_ch1
* [23:22] cs0_row_ch1
* [21:20] cs1_row_ch1
* [19:18] bw_ch1
* [17:16] dbw_ch1;
* [15:13] ddrtype
* [12] channelnum
* [11] rank_ch0
* [10:9] col_ch0
* [8] bk_ch0
* [7:6] cs0_row_ch0
* [5:4] cs1_row_ch0
* [3:2] bw_ch0
* [1:0] dbw_ch0
*/
#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1)
#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
#define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1)
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7)
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1))
#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16))
#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16))
#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16))
#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16))
#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16))
#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16))
#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16))
#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3))
#define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \
(0x1f<<(10+16))|((n)<<10))
#define CTL_REG_NUM 332
#define PHY_REG_NUM 959
#define PI_REG_NUM 200
enum {
DDR3 = 3,
LPDDR2 = 5,
@ -259,6 +159,7 @@ struct rk3399_sdram_params {
struct rk3399_ddr_pctl_regs pctl_regs;
struct rk3399_ddr_pi_regs pi_regs;
struct rk3399_ddr_publ_regs phy_regs;
uint32_t rx_cal_dqs[2][4];
};
extern __sramdata struct rk3399_sdram_params sdram_config;

151
plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
View File

@ -267,21 +267,24 @@ static void ddr3_get_parameter(struct timing_related_config *timing_config,
break;
}
switch (timing_config->dramodt) {
case 60:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60;
break;
case 40:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40;
break;
case 120:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120;
break;
case 0:
default:
if (timing_config->odt)
switch (timing_config->dramodt) {
case 60:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60;
break;
case 40:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40;
break;
case 120:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120;
break;
case 0:
default:
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS;
break;
}
else
pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS;
break;
}
pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl);
pdram_timing->mr[3] = 0;
@ -664,6 +667,9 @@ static void lpddr2_get_parameter(struct timing_related_config *timing_config,
#define LPDDR3_TADR (20) /* ns */
#define LPDDR3_TMRZ (3) /* ns */
/* FSP */
#define LPDDR3_TFC_LONG (250) /* ns */
/*
* Description: depend on input parameter "timing_config",
* and calculate all lpddr3
@ -751,18 +757,21 @@ static void lpddr3_get_parameter(struct timing_related_config *timing_config,
break;
}
pdram_timing->mr[0] = 0;
switch (timing_config->dramodt) {
case 60:
pdram_timing->mr11 = LPDDR3_ODT_60;
break;
case 120:
pdram_timing->mr11 = LPDDR3_ODT_120;
break;
case 240:
default:
pdram_timing->mr11 = LPDDR3_ODT_240;
break;
}
if (timing_config->odt)
switch (timing_config->dramodt) {
case 60:
pdram_timing->mr11 = LPDDR3_ODT_60;
break;
case 120:
pdram_timing->mr11 = LPDDR3_ODT_120;
break;
case 240:
default:
pdram_timing->mr11 = LPDDR3_ODT_240;
break;
}
else
pdram_timing->mr11 = LPDDR3_ODT_DIS;
pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000;
pdram_timing->tinit2 = LPDDR3_TINIT2;
@ -874,6 +883,9 @@ static void lpddr3_get_parameter(struct timing_related_config *timing_config,
pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000;
pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000;
pdram_timing->tcacd = pdram_timing->tadr + 2;
/* FSP */
pdram_timing->tfc_long = (LPDDR3_TFC_LONG * nmhz + 999) / 1000;
}
#define LPDDR4_TINIT1 (200000) /* 200us */
@ -1113,47 +1125,52 @@ static void lpddr4_get_parameter(struct timing_related_config *timing_config,
break;
}
pdram_timing->mr[0] = 0;
switch (timing_config->dramodt) {
case 240:
tmp = LPDDR4_DQODT_240;
break;
case 120:
tmp = LPDDR4_DQODT_120;
break;
case 80:
tmp = LPDDR4_DQODT_80;
break;
case 60:
tmp = LPDDR4_DQODT_60;
break;
case 48:
tmp = LPDDR4_DQODT_48;
break;
case 40:
default:
tmp = LPDDR4_DQODT_40;
break;
}
switch (timing_config->caodt) {
case 240:
pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp;
break;
case 120:
pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp;
break;
case 80:
pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp;
break;
case 60:
pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp;
break;
case 48:
pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp;
break;
case 40:
default:
pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp;
break;
if (timing_config->odt) {
switch (timing_config->dramodt) {
case 240:
tmp = LPDDR4_DQODT_240;
break;
case 120:
tmp = LPDDR4_DQODT_120;
break;
case 80:
tmp = LPDDR4_DQODT_80;
break;
case 60:
tmp = LPDDR4_DQODT_60;
break;
case 48:
tmp = LPDDR4_DQODT_48;
break;
case 40:
default:
tmp = LPDDR4_DQODT_40;
break;
}
switch (timing_config->caodt) {
case 240:
pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp;
break;
case 120:
pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp;
break;
case 80:
pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp;
break;
case 60:
pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp;
break;
case 48:
pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp;
break;
case 40:
default:
pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp;
break;
}
} else {
pdram_timing->mr11 = LPDDR4_CAODT_DIS | tmp;
}
pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000;

31
plat/rockchip/rk3399/drivers/dram/suspend.c
View File

@ -34,6 +34,7 @@
#include <dram.h>
#include <pmu_regs.h>
#include <rk3399_def.h>
#include <secure.h>
#include <soc.h>
#include <suspend.h>
@ -571,14 +572,15 @@ static __sramfunc void pctl_cfg(uint32_t ch,
sram_regcpy(PHY_REG(ch, 768), (uintptr_t)&params_phy[768], 38);
}
static __sramfunc int dram_switch_to_phy_index1(
static __sramfunc int dram_switch_to_next_index(
struct rk3399_sdram_params *sdram_params)
{
uint32_t ch, ch_count;
uint32_t fn = ((mmio_read_32(CTL_REG(0, 111)) >> 16) + 1) & 0x1;
mmio_write_32(CIC_BASE + CIC_CTRL0,
(((0x3 << 4) | (1 << 2) | 1) << 16) |
(1 << 4) | (1 << 2) | 1);
(fn << 4) | (1 << 2) | 1);
while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)))
;
@ -591,7 +593,7 @@ static __sramfunc int dram_switch_to_phy_index1(
/* LPDDR4 f2 cann't do training, all training will fail */
for (ch = 0; ch < ch_count; ch++) {
mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1,
1 << 8);
fn << 8);
/* data_training failed */
if (data_training(ch, sdram_params, PI_FULL_TRAINING))
@ -609,6 +611,7 @@ static __sramfunc int pctl_start(uint32_t channel_mask,
struct rk3399_sdram_params *sdram_params)
{
uint32_t count;
uint32_t byte;
mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT);
mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT);
@ -640,6 +643,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask,
}
mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT);
/* Restore the PHY_RX_CAL_DQS value */
for (byte = 0; byte < 4; byte++)
mmio_clrsetbits_32(PHY_REG(0, 57 + 128 * byte),
0xfff << 16,
sdram_params->rx_cal_dqs[0][byte]);
}
if (channel_mask & (1 << 1)) {
count = 0;
@ -653,6 +662,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask,
}
mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT);
/* Restore the PHY_RX_CAL_DQS value */
for (byte = 0; byte < 4; byte++)
mmio_clrsetbits_32(PHY_REG(1, 57 + 128 * byte),
0xfff << 16,
sdram_params->rx_cal_dqs[1][byte]);
}
return 0;
@ -665,7 +680,7 @@ void dmc_save(void)
uint32_t *params_pi;
uint32_t *params_phy;
uint32_t refdiv, postdiv2, postdiv1, fbdiv;
uint32_t tmp;
uint32_t tmp, ch, byte;
params_ctl = sdram_params->pctl_regs.denali_ctl;
params_pi = sdram_params->pi_regs.denali_pi;
@ -705,6 +720,12 @@ void dmc_save(void)
sram_regcpy((uintptr_t)&params_phy[768], PHY_REG(0, 768), 38);
sram_regcpy((uintptr_t)&params_phy[896], PHY_REG(0, 896), 63);
for (ch = 0; ch < sdram_params->num_channels; ch++) {
for (byte = 0; byte < 4; byte++)
sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) &
mmio_read_32(PHY_REG(ch, 57 + byte * 128));
}
/* set DENALI_PHY_957_DATA.PHY_DLL_RST_EN = 0x1 */
params_phy[957] &= ~(0x3 << 24);
params_phy[957] |= 1 << 24;
@ -754,5 +775,5 @@ retry:
dram_all_config(sdram_params);
/* Switch to index 1 and prepare for DDR frequency switch. */
dram_switch_to_phy_index1(sdram_params);
dram_switch_to_next_index(sdram_params);
}

40
plat/rockchip/rk3399/drivers/m0/Makefile
View File

@ -46,32 +46,29 @@ export Q
.SUFFIXES:
INCLUDES += -Iinclude/
INCLUDES += -Iinclude/ \
-I../../include/shared/
# NOTE: Add C source files here
C_SOURCES := src/startup.c \
src/main.c
src/main.c \
src/suspend.c \
src/dram.c \
src/stopwatch.c
# Flags definition
CFLAGS := -g
ASFLAGS := -g -Wa,--gdwarf-2
ASFLAGS += -mcpu=$(ARCH) -mthumb -Wall -ffunction-sections -O3
CFLAGS += -mcpu=$(ARCH) -mthumb -Wall -ffunction-sections -O3
LDFLAGS := -mcpu=$(ARCH) -mthumb -g -nostartfiles -nostdlib -O3
LDFLAGS += -Wl,--gc-sections -Wl,--build-id=none
COMMON_FLAGS := -g -mcpu=$(ARCH) -mthumb -Wall -O3 -nostdlib -mfloat-abi=soft
CFLAGS := -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-common
ASFLAGS := -Wa,--gdwarf-2
LDFLAGS := -Wl,--gc-sections -Wl,--build-id=none
# Cross tool
CC := ${M0_CROSS_COMPILE}gcc
CPP := ${M0_CROSS_COMPILE}cpp
AS := ${M0_CROSS_COMPILE}gcc
AR := ${M0_CROSS_COMPILE}ar
LD := ${M0_CROSS_COMPILE}ld
OC := ${M0_CROSS_COMPILE}objcopy
OD := ${M0_CROSS_COMPILE}objdump
NM := ${M0_CROSS_COMPILE}nm
PP := ${M0_CROSS_COMPILE}gcc -E ${CFLAGS}
# NOTE: The line continuation '\' is required in the next define otherwise we
# end up with a line-feed characer at the end of the last c filename.
@ -83,10 +80,11 @@ endef
SOURCES := $(C_SOURCES)
OBJS := $(addprefix $(BUILD)/,$(call SOURCES_TO_OBJS,$(SOURCES)))
LINKERFILE := src/rk3399m0.ld
LINKERFILE := $(BUILD)/$(PLAT_M0).ld
MAPFILE := $(BUILD)/$(PLAT_M0).map
ELF := $(BUILD)/$(PLAT_M0).elf
BIN := $(BUILD)/$(PLAT_M0).bin
LINKERFILE_SRC := src/$(PLAT_M0).ld.S
# Function definition related compilation
define MAKE_C
@ -95,7 +93,7 @@ $(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
$(OBJ) : $(2)
@echo " CC $$<"
$$(Q)$$(CC) $$(CFLAGS) $$(INCLUDES) -MMD -MT $$@ -c $$< -o $$@
$$(Q)$$(CC) $$(COMMON_FLAGS) $$(CFLAGS) $$(INCLUDES) -MMD -MT $$@ -c $$< -o $$@
endef
define MAKE_S
@ -103,7 +101,7 @@ $(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
$(OBJ) : $(2)
@echo " AS $$<"
$$(Q)$$(AS) $$(ASFLAGS) -c $$< -o $$@
$$(Q)$$(CC) -x assembler-with-cpp $$(COMMON_FLAGS) $$(ASFLAGS) -c $$< -o $$@
endef
define MAKE_OBJS
@ -118,13 +116,15 @@ define MAKE_OBJS
$(and $(REMAIN),$(error Unexpected source files present: $(REMAIN)))
endef
.PHONY: all
all: $(BIN)
.DEFAULT_GOAL := $(BIN)
$(LINKERFILE): $(LINKERFILE_SRC)
$(CC) $(COMMON_FLAGS) $(INCLUDES) -P -E -D__LINKER__ -MMD -MF $@.d -MT $@ -o $@ $<
-include $(LINKERFILE).d
$(ELF) : $(OBJS) $(LINKERFILE)
@echo " LD $@"
$(Q)$(CC) -o $@ $(LDFLAGS) -Wl,-Map=$(MAPFILE) -Wl,-T$(LINKERFILE) \
$(OBJS)
$(Q)$(CC) -o $@ $(COMMON_FLAGS) $(LDFLAGS) -Wl,-Map=$(MAPFILE) -Wl,-T$(LINKERFILE) $(OBJS)
$(BIN) : $(ELF)
@echo " BIN $@"

13
plat/rockchip/rk3399/drivers/pmu/rk3399m0.h → plat/rockchip/rk3399/drivers/m0/include/addressmap.h
View File

@ -28,13 +28,12 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __RK3399M0_H__
#define __RK3399M0_H__
#ifndef __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__
#define __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__
/* pmu_fw.c */
extern char rk3399m0_bin[];
extern char rk3399m0_bin_end[];
#include <addressmap_shared.h>
#define M0_BINCODE_BASE ((uintptr_t)rk3399m0_bin)
/* Registers base address for M0 */
#define MMIO_BASE 0x40000000
#endif /* __RK3399M0_H__ */
#endif /* __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__ */

27
plat/rockchip/rk3399/drivers/m0/include/rk3399_mcu.h
View File

@ -31,11 +31,28 @@
#ifndef __RK3399_MCU_H__
#define __RK3399_MCU_H__
#define readl(c) ({unsigned int __v = \
(*(volatile unsigned int *)(c)); __v; })
#define writel(v, c) ((*(volatile unsigned int *) (c)) = (v))
#include <addressmap.h>
#define MCU_BASE 0x40000000
#define PMU_BASE (MCU_BASE + 0x07310000)
typedef unsigned int uint32_t;
#define mmio_read_32(c) ({unsigned int __v = \
(*(volatile unsigned int *)(c)); __v; })
#define mmio_write_32(c, v) ((*(volatile unsigned int *)(c)) = (v))
#define mmio_clrbits_32(addr, clear) \
mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)))
#define mmio_setbits_32(addr, set) \
mmio_write_32(addr, (mmio_read_32(addr)) | (set))
#define mmio_clrsetbits_32(addr, clear, set) \
mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
void handle_suspend(void);
void handle_dram(void);
void stopwatch_init_usecs_expire(unsigned int usecs);
int stopwatch_expired(void);
void stopwatch_reset(void);
#endif /* __RK3399_MCU_H__ */

103
plat/rockchip/rk3399/drivers/m0/src/dram.c Normal file
View File

@ -0,0 +1,103 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <dram_regs.h>
#include <m0_param.h>
#include <pmu_bits.h>
#include <pmu_regs.h>
#include "misc_regs.h"
#include "rk3399_mcu.h"
static uint32_t gatedis_con0;
static void idle_port(void)
{
gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0);
mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff);
mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
(1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1));
while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) &
((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) !=
((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0)))
continue;
}
static void deidle_port(void)
{
mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
(1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1));
while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) &
((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0)))
continue;
/* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0);
}
static void ddr_set_pll(void)
{
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE));
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1));
mmio_write_32(CRU_BASE + CRU_DPLL_CON0,
mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0));
mmio_write_32(CRU_BASE + CRU_DPLL_CON1,
mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1));
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0));
while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0)
continue;
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE));
}
void handle_dram(void)
{
mmio_setbits_32(PHY_REG(0, 927), (1 << 22));
mmio_setbits_32(PHY_REG(1, 927), (1 << 22));
idle_port();
mmio_write_32(CIC_BASE + CIC_CTRL0,
(((0x3 << 4) | (1 << 2) | 1) << 16) |
(1 << 2) | 1 |
mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT));
while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0)
continue;
ddr_set_pll();
mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002);
while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0)
continue;
deidle_port();
mmio_clrbits_32(PHY_REG(0, 927), (1 << 22));
mmio_clrbits_32(PHY_REG(1, 927), (1 << 22));
}

46
plat/rockchip/rk3399/drivers/m0/src/main.c
View File

@ -28,44 +28,24 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <m0_param.h>
#include "rk3399_mcu.h"
#define PMU_PWRMODE_CON 0x20
#define PMU_POWER_ST 0x78
#define M0_SCR 0xe000ed10 /* System Control Register (SCR) */
#define SCR_SLEEPDEEP_SHIFT (1 << 2)
static void system_wakeup(void)
__attribute__((noreturn)) void main(void)
{
unsigned int status_value;
unsigned int mode_con;
while (1) {
status_value = readl(PMU_BASE + PMU_POWER_ST);
if (status_value) {
mode_con = readl(PMU_BASE + PMU_PWRMODE_CON);
writel(mode_con & (~0x01),
PMU_BASE + PMU_PWRMODE_CON);
return;
}
switch (mmio_read_32(PARAM_ADDR + PARAM_M0_FUNC)) {
case M0_FUNC_SUSPEND:
handle_suspend();
break;
case M0_FUNC_DRAM:
handle_dram();
break;
default:
break;
}
}
int main(void)
{
unsigned int reg_src;
system_wakeup();
reg_src = readl(M0_SCR);
/* m0 enter deep sleep mode */
writel(reg_src | SCR_SLEEPDEEP_SHIFT, M0_SCR);
mmio_write_32(PARAM_ADDR + PARAM_M0_DONE, M0_DONE_FLAG);
for (;;)
__asm volatile("wfi");
return 0;
__asm__ volatile ("wfi");
}

4
plat/rockchip/rk3399/drivers/m0/src/rk3399m0.ld → plat/rockchip/rk3399/drivers/m0/src/rk3399m0.ld.S
View File

@ -28,12 +28,16 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <m0_param.h>
OUTPUT_FORMAT("elf32-littlearm")
SECTIONS {
.m0_bin 0 : {
KEEP(*(.isr_vector))
ASSERT(. == 0xc0, "ISR vector has the wrong size.");
ASSERT(. == PARAM_ADDR, "M0 params should go right behind ISR table.");
. += PARAM_M0_SIZE;
*(.text*)
*(.rodata*)
*(.data*)

98
plat/rockchip/rk3399/drivers/m0/src/stopwatch.c Normal file
View File

@ -0,0 +1,98 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <m0_param.h>
#include "rk3399_mcu.h"
/* use 24MHz SysTick */
#define US_TO_CYCLE(US) (US * 24)
#define SYST_CST 0xe000e010
/* enable counter */
#define ENABLE (1 << 0)
/* count down to 0 does not cause SysTick exception to pend */
#define TICKINT (1 << 1)
/* core clock used for SysTick */
#define CLKSOURCE (1 << 2)
#define COUNTFLAG (1 << 16)
#define SYST_RVR 0xe000e014
#define MAX_VALUE 0xffffff
#define MAX_USECS (MAX_VALUE / US_TO_CYCLE(1))
#define SYST_CVR 0xe000e018
#define SYST_CALIB 0xe000e01c
unsigned int remaining_usecs;
static inline void stopwatch_set_usecs(void)
{
unsigned int cycle;
unsigned int usecs = MIN(MAX_USECS, remaining_usecs);
remaining_usecs -= usecs;
cycle = US_TO_CYCLE(usecs);
mmio_write_32(SYST_RVR, cycle);
mmio_write_32(SYST_CVR, 0);
mmio_write_32(SYST_CST, ENABLE | TICKINT | CLKSOURCE);
}
void stopwatch_init_usecs_expire(unsigned int usecs)
{
/*
* Enter an inifite loop if the stopwatch is in use. This will allow the
* state to be analyzed with a debugger.
*/
if (mmio_read_32(SYST_CST) & ENABLE)
while (1)
;
remaining_usecs = usecs;
stopwatch_set_usecs();
}
int stopwatch_expired(void)
{
int val = mmio_read_32(SYST_CST);
if ((val & COUNTFLAG) || !(val & ENABLE)) {
if (!remaining_usecs)
return 1;
stopwatch_set_usecs();
}
return 0;
}
void stopwatch_reset(void)
{
mmio_clrbits_32(SYST_CST, ENABLE);
remaining_usecs = 0;
}

52
plat/rockchip/rk3399/drivers/m0/src/suspend.c Normal file
View File

@ -0,0 +1,52 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <pmu_regs.h>
#include "rk3399_mcu.h"
#define M0_SCR 0xe000ed10 /* System Control Register (SCR) */
#define SCR_SLEEPDEEP_SHIFT (1 << 2)
void handle_suspend(void)
{
unsigned int status_value;
while (1) {
status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST);
if (status_value) {
mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01);
return;
}
}
/* m0 enter deep sleep mode */
mmio_setbits_32(M0_SCR, SCR_SLEEPDEEP_SHIFT);
}

121
plat/rockchip/rk3399/drivers/pmu/m0_ctl.c Normal file
View File

@ -0,0 +1,121 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <assert.h>
#include <debug.h>
#include <delay_timer.h>
#include <mmio.h>
#include <m0_ctl.h>
#include <plat_private.h>
#include <rk3399_def.h>
#include <secure.h>
#include <soc.h>
void m0_init(void)
{
/* secure config for M0 */
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7));
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12));
/* set the execute address for M0 */
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff,
0xffff, 0));
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf,
0xf, 0));
/* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02);
/*
* To switch the parent to xin24M and div == 1,
*
* We need to close most of the PLLs and clocks except the OSC 24MHz
* durning suspend, and this should be enough to supplies the ddrfreq,
* For the simple handle, we just keep the fixed 24MHz to supply the
* suspend and ddrfreq directly.
*/
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0,
BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8));
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5));
}
void m0_start(void)
{
/* enable clocks for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
BITS_WITH_WMASK(0x0, 0xf, 0));
/* clean the PARAM_M0_DONE flag, mean that M0 will start working */
mmio_write_32(M0_PARAM_ADDR + PARAM_M0_DONE, 0);
dmbst();
mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
BITS_WITH_WMASK(0x0, 0x4, 0));
udelay(5);
/* start M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
BITS_WITH_WMASK(0x0, 0x20, 0));
dmbst();
}
void m0_stop(void)
{
/* stop M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
BITS_WITH_WMASK(0x24, 0x24, 0));
/* disable clocks for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
BITS_WITH_WMASK(0xf, 0xf, 0));
}
void m0_wait_done(void)
{
do {
/*
* Don't starve the M0 for access to SRAM, so delay before
* reading the PARAM_M0_DONE value again.
*/
udelay(5);
dsb();
} while (mmio_read_32(M0_PARAM_ADDR + PARAM_M0_DONE) != M0_DONE_FLAG);
/*
* Let the M0 settle into WFI before we leave. This is so we don't reset
* the M0 in a bad spot which can cause problems with the M0.
*/
udelay(10);
dsb();
}

47
plat/rockchip/rk3399/drivers/pmu/m0_ctl.h Normal file
View File

@ -0,0 +1,47 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __M0_CTL_H__
#define __M0_CTL_H__
#include <m0_param.h>
#define M0_BINCODE_BASE ((uintptr_t)rk3399m0_bin)
#define M0_PARAM_ADDR (M0_BINCODE_BASE + PARAM_ADDR)
/* pmu_fw.c */
extern char rk3399m0_bin[];
extern char rk3399m0_bin_end[];
extern void m0_init(void);
extern void m0_start(void);
extern void m0_stop(void);
extern void m0_wait_done(void);
#endif /* __M0_CTL_H__ */

51
plat/rockchip/rk3399/drivers/pmu/pmu.c
View File

@ -33,21 +33,23 @@
#include <bakery_lock.h>
#include <debug.h>
#include <delay_timer.h>
#include <dfs.h>
#include <errno.h>
#include <gpio.h>
#include <mmio.h>
#include <m0_ctl.h>
#include <platform.h>
#include <platform_def.h>
#include <plat_params.h>
#include <plat_private.h>
#include <rk3399_def.h>
#include <pmu_sram.h>
#include <secure.h>
#include <soc.h>
#include <pmu.h>
#include <pmu_com.h>
#include <pwm.h>
#include <bl31.h>
#include <rk3399m0.h>
#include <suspend.h>
DEFINE_BAKERY_LOCK(rockchip_pd_lock);
@ -1065,36 +1067,10 @@ static void resume_gpio(void)
}
}
static void m0_clock_init(void)
static void m0_configure_suspend(void)
{
/* enable clocks for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
BITS_WITH_WMASK(0x0, 0x2f, 0));
/* switch the parent to xin24M and div == 1 */
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0,
BIT_WITH_WMSK(15) | BITS_WITH_WMASK(0x0, 0x1f, 8));
/* start M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
BITS_WITH_WMASK(0x0, 0x24, 0));
/* gating disable for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, BIT_WITH_WMSK(1));
}
static void m0_reset(void)
{
/* stop M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0,
BITS_WITH_WMASK(0x24, 0x24, 0));
/* recover gating bit for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, WMSK_BIT(1));
/* disable clocks for M0 */
mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2,
BITS_WITH_WMASK(0x2f, 0x2f, 0));
/* set PARAM to M0_FUNC_SUSPEND */
mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_SUSPEND);
}
static int sys_pwr_domain_suspend(void)
@ -1102,6 +1078,7 @@ static int sys_pwr_domain_suspend(void)
uint32_t wait_cnt = 0;
uint32_t status = 0;
ddr_prepare_for_sys_suspend();
dmc_save();
pmu_scu_b_pwrdn();
@ -1117,11 +1094,12 @@ static int sys_pwr_domain_suspend(void)
sys_slp_config();
m0_clock_init();
m0_configure_suspend();
m0_start();
pmu_sgrf_rst_hld();
mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1),
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
(PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) |
CPU_BOOT_ADDR_WMASK);
@ -1173,7 +1151,7 @@ static int sys_pwr_domain_resume(void)
udelay(300);
enable_dvfs_plls();
secure_watchdog_restore();
secure_watchdog_enable();
/* restore clk_ddrc_bpll_src_en gate */
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),
@ -1189,7 +1167,7 @@ static int sys_pwr_domain_resume(void)
mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff);
mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1),
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
(cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) |
CPU_BOOT_ADDR_WMASK);
@ -1241,8 +1219,9 @@ static int sys_pwr_domain_resume(void)
BIT(PMU_CLR_GIC));
plat_rockchip_gic_cpuif_enable();
m0_stop();
m0_reset();
ddr_prepare_for_sys_resume();
return 0;
}
@ -1328,7 +1307,7 @@ void plat_rockchip_pmu_init(void)
psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff;
/* config cpu's warm boot address */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1),
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
(cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) |
CPU_BOOT_ADDR_WMASK);
mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE);

688
plat/rockchip/rk3399/drivers/pmu/pmu.h
View File

@ -31,6 +31,7 @@
#ifndef __PMU_H__
#define __PMU_H__
#include <pmu_bits.h>
#include <pmu_regs.h>
#include <soc.h>
@ -67,693 +68,6 @@ enum pmu_core_pwrst_shift {
#define CKECK_WFI_MSK 0x10
#define CKECK_WFEI_MSK 0x11
enum pmu_powerdomain_id {
PD_CPUL0 = 0,
PD_CPUL1,
PD_CPUL2,
PD_CPUL3,
PD_CPUB0,
PD_CPUB1,
PD_SCUL,
PD_SCUB,
PD_TCPD0,
PD_TCPD1,
PD_CCI,
PD_PERILP,
PD_PERIHP,
PD_CENTER,
PD_VIO,
PD_GPU,
PD_VCODEC,
PD_VDU,
PD_RGA,
PD_IEP,
PD_VO,
PD_ISP0 = 22,
PD_ISP1,
PD_HDCP,
PD_GMAC,
PD_EMMC,
PD_USB3,
PD_EDP,
PD_GIC,
PD_SD,
PD_SDIOAUDIO,
PD_END
};
enum powerdomain_state {
PMU_POWER_ON = 0,
PMU_POWER_OFF,
};
enum pmu_bus_id {
BUS_ID_GPU = 0,
BUS_ID_PERILP,
BUS_ID_PERIHP,
BUS_ID_VCODEC,
BUS_ID_VDU,
BUS_ID_RGA,
BUS_ID_IEP,
BUS_ID_VOPB,
BUS_ID_VOPL,
BUS_ID_ISP0,
BUS_ID_ISP1,
BUS_ID_HDCP,
BUS_ID_USB3,
BUS_ID_PERILPM0,
BUS_ID_CENTER,
BUS_ID_CCIM0,
BUS_ID_CCIM1,
BUS_ID_VIO,
BUS_ID_MSCH0,
BUS_ID_MSCH1,
BUS_ID_ALIVE,
BUS_ID_PMU,
BUS_ID_EDP,
BUS_ID_GMAC,
BUS_ID_EMMC,
BUS_ID_CENTER1,
BUS_ID_PMUM0,
BUS_ID_GIC,
BUS_ID_SD,
BUS_ID_SDIOAUDIO,
};
enum pmu_bus_state {
BUS_ACTIVE,
BUS_IDLE,
};
/* pmu_cpuapm bit */
enum pmu_cores_pm_by_wfi {
core_pm_en = 0,
core_pm_int_wakeup_en,
core_pm_resv,
core_pm_sft_wakeup_en
};
enum pmu_wkup_cfg0 {
PMU_GPIO0A_POSE_WKUP_EN = 0,
PMU_GPIO0B_POSE_WKUP_EN = 8,
PMU_GPIO0C_POSE_WKUP_EN = 16,
PMU_GPIO0D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg1 {
PMU_GPIO0A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO0B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO0C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO0D_NEGEDGE_WKUP_EN = 24,
};
enum pmu_wkup_cfg2 {
PMU_GPIO1A_POSE_WKUP_EN = 0,
PMU_GPIO1B_POSE_WKUP_EN = 7,
PMU_GPIO1C_POSE_WKUP_EN = 16,
PMU_GPIO1D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg3 {
PMU_GPIO1A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO1B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO1C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO1D_NEGEDGE_WKUP_EN = 24,
};
/* pmu_wkup_cfg4 */
enum pmu_wkup_cfg4 {
PMU_CLUSTER_L_WKUP_EN = 0,
PMU_CLUSTER_B_WKUP_EN,
PMU_GPIO_WKUP_EN,
PMU_SDIO_WKUP_EN,
PMU_SDMMC_WKUP_EN,
PMU_TIMER_WKUP_EN = 6,
PMU_USBDEV_WKUP_EN,
PMU_SFT_WKUP_EN,
PMU_M0_WDT_WKUP_EN,
PMU_TIMEOUT_WKUP_EN,
PMU_PWM_WKUP_EN,
PMU_PCIE_WKUP_EN = 13,
};
enum pmu_pwrdn_con {
PMU_A53_L0_PWRDWN_EN = 0,
PMU_A53_L1_PWRDWN_EN,
PMU_A53_L2_PWRDWN_EN,
PMU_A53_L3_PWRDWN_EN,
PMU_A72_B0_PWRDWN_EN,
PMU_A72_B1_PWRDWN_EN,
PMU_SCU_L_PWRDWN_EN,
PMU_SCU_B_PWRDWN_EN,
PMU_TCPD0_PWRDWN_EN,
PMU_TCPD1_PWRDWN_EN,
PMU_CCI_PWRDWN_EN,
PMU_PERILP_PWRDWN_EN,
PMU_PERIHP_PWRDWN_EN,
PMU_CENTER_PWRDWN_EN,
PMU_VIO_PWRDWN_EN,
PMU_GPU_PWRDWN_EN,
PMU_VCODEC_PWRDWN_EN,
PMU_VDU_PWRDWN_EN,
PMU_RGA_PWRDWN_EN,
PMU_IEP_PWRDWN_EN,
PMU_VO_PWRDWN_EN,
PMU_ISP0_PWRDWN_EN = 22,
PMU_ISP1_PWRDWN_EN,
PMU_HDCP_PWRDWN_EN,
PMU_GMAC_PWRDWN_EN,
PMU_EMMC_PWRDWN_EN,
PMU_USB3_PWRDWN_EN,
PMU_EDP_PWRDWN_EN,
PMU_GIC_PWRDWN_EN,
PMU_SD_PWRDWN_EN,
PMU_SDIOAUDIO_PWRDWN_EN,
};
enum pmu_pwrdn_st {
PMU_A53_L0_PWRDWN_ST = 0,
PMU_A53_L1_PWRDWN_ST,
PMU_A53_L2_PWRDWN_ST,
PMU_A53_L3_PWRDWN_ST,
PMU_A72_B0_PWRDWN_ST,
PMU_A72_B1_PWRDWN_ST,
PMU_SCU_L_PWRDWN_ST,
PMU_SCU_B_PWRDWN_ST,
PMU_TCPD0_PWRDWN_ST,
PMU_TCPD1_PWRDWN_ST,
PMU_CCI_PWRDWN_ST,
PMU_PERILP_PWRDWN_ST,
PMU_PERIHP_PWRDWN_ST,
PMU_CENTER_PWRDWN_ST,
PMU_VIO_PWRDWN_ST,
PMU_GPU_PWRDWN_ST,
PMU_VCODEC_PWRDWN_ST,
PMU_VDU_PWRDWN_ST,
PMU_RGA_PWRDWN_ST,
PMU_IEP_PWRDWN_ST,
PMU_VO_PWRDWN_ST,
PMU_ISP0_PWRDWN_ST = 22,
PMU_ISP1_PWRDWN_ST,
PMU_HDCP_PWRDWN_ST,
PMU_GMAC_PWRDWN_ST,
PMU_EMMC_PWRDWN_ST,
PMU_USB3_PWRDWN_ST,
PMU_EDP_PWRDWN_ST,
PMU_GIC_PWRDWN_ST,
PMU_SD_PWRDWN_ST,
PMU_SDIOAUDIO_PWRDWN_ST,
};
enum pmu_pll_con {
PMU_PLL_PD_CFG = 0,
PMU_SFT_PLL_PD = 8,
};
enum pmu_pwermode_con {
PMU_PWR_MODE_EN = 0,
PMU_WKUP_RST_EN,
PMU_INPUT_CLAMP_EN,
PMU_OSC_DIS,
PMU_ALIVE_USE_LF,
PMU_PMU_USE_LF,
PMU_POWER_OFF_REQ_CFG,
PMU_CHIP_PD_EN,
PMU_PLL_PD_EN,
PMU_CPU0_PD_EN,
PMU_L2_FLUSH_EN,
PMU_L2_IDLE_EN,
PMU_SCU_PD_EN,
PMU_CCI_PD_EN,
PMU_PERILP_PD_EN,
PMU_CENTER_PD_EN,
PMU_SREF0_ENTER_EN,
PMU_DDRC0_GATING_EN,
PMU_DDRIO0_RET_EN,
PMU_DDRIO0_RET_DE_REQ,
PMU_SREF1_ENTER_EN,
PMU_DDRC1_GATING_EN,
PMU_DDRIO1_RET_EN,
PMU_DDRIO1_RET_DE_REQ,
PMU_CLK_CENTER_SRC_GATE_EN = 26,
PMU_CLK_PERILP_SRC_GATE_EN,
PMU_CLK_CORE_SRC_GATE_EN,
PMU_DDRIO_RET_HW_DE_REQ,
PMU_SLP_OUTPUT_CFG,
PMU_MAIN_CLUSTER,
};
enum pmu_sft_con {
PMU_WKUP_SFT = 0,
PMU_INPUT_CLAMP_CFG,
PMU_OSC_DIS_CFG,
PMU_PMU_LF_EN_CFG,
PMU_ALIVE_LF_EN_CFG,
PMU_24M_EN_CFG,
PMU_DBG_PWRUP_L0_CFG,
PMU_WKUP_SFT_M0,
PMU_DDRCTL0_C_SYSREQ_CFG,
PMU_DDR0_IO_RET_CFG,
PMU_DDRCTL1_C_SYSREQ_CFG = 12,
PMU_DDR1_IO_RET_CFG,
DBG_PWRUP_B0_CFG = 15,
DBG_NOPWERDWN_L0_EN,
DBG_NOPWERDWN_L1_EN,
DBG_NOPWERDWN_L2_EN,
DBG_NOPWERDWN_L3_EN,
DBG_PWRUP_REQ_L_EN = 20,
CLUSTER_L_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_L,
ACINACTM_CLUSTER_L_CFG,
DBG_NO_PWERDWN_B0_EN,
DBG_NO_PWERDWN_B1_EN,
DBG_PWRUP_REQ_B_EN = 28,
CLUSTER_B_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_B,
ACINACTM_CLUSTER_B_CFG,
};
enum pmu_int_con {
PMU_PMU_INT_EN = 0,
PMU_PWRMD_WKUP_INT_EN,
PMU_WKUP_GPIO0_NEG_INT_EN,
PMU_WKUP_GPIO0_POS_INT_EN,
PMU_WKUP_GPIO1_NEG_INT_EN,
PMU_WKUP_GPIO1_POS_INT_EN,
};
enum pmu_int_st {
PMU_PWRMD_WKUP_INT_ST = 1,
PMU_WKUP_GPIO0_NEG_INT_ST,
PMU_WKUP_GPIO0_POS_INT_ST,
PMU_WKUP_GPIO1_NEG_INT_ST,
PMU_WKUP_GPIO1_POS_INT_ST,
};
enum pmu_gpio0_pos_int_con {
PMU_GPIO0A_POS_INT_EN = 0,
PMU_GPIO0B_POS_INT_EN = 8,
PMU_GPIO0C_POS_INT_EN = 16,
PMU_GPIO0D_POS_INT_EN = 24,
};
enum pmu_gpio0_neg_int_con {
PMU_GPIO0A_NEG_INT_EN = 0,
PMU_GPIO0B_NEG_INT_EN = 8,
PMU_GPIO0C_NEG_INT_EN = 16,
PMU_GPIO0D_NEG_INT_EN = 24,
};
enum pmu_gpio1_pos_int_con {
PMU_GPIO1A_POS_INT_EN = 0,
PMU_GPIO1B_POS_INT_EN = 8,
PMU_GPIO1C_POS_INT_EN = 16,
PMU_GPIO1D_POS_INT_EN = 24,
};
enum pmu_gpio1_neg_int_con {
PMU_GPIO1A_NEG_INT_EN = 0,
PMU_GPIO1B_NEG_INT_EN = 8,
PMU_GPIO1C_NEG_INT_EN = 16,
PMU_GPIO1D_NEG_INT_EN = 24,
};
enum pmu_gpio0_pos_int_st {
PMU_GPIO0A_POS_INT_ST = 0,
PMU_GPIO0B_POS_INT_ST = 8,
PMU_GPIO0C_POS_INT_ST = 16,
PMU_GPIO0D_POS_INT_ST = 24,
};
enum pmu_gpio0_neg_int_st {
PMU_GPIO0A_NEG_INT_ST = 0,
PMU_GPIO0B_NEG_INT_ST = 8,
PMU_GPIO0C_NEG_INT_ST = 16,
PMU_GPIO0D_NEG_INT_ST = 24,
};
enum pmu_gpio1_pos_int_st {
PMU_GPIO1A_POS_INT_ST = 0,
PMU_GPIO1B_POS_INT_ST = 8,
PMU_GPIO1C_POS_INT_ST = 16,
PMU_GPIO1D_POS_INT_ST = 24,
};
enum pmu_gpio1_neg_int_st {
PMU_GPIO1A_NEG_INT_ST = 0,
PMU_GPIO1B_NEG_INT_ST = 8,
PMU_GPIO1C_NEG_INT_ST = 16,
PMU_GPIO1D_NEG_INT_ST = 24,
};
/* pmu power down configure register 0x0050 */
enum pmu_pwrdn_inten {
PMU_A53_L0_PWR_SWITCH_INT_EN = 0,
PMU_A53_L1_PWR_SWITCH_INT_EN,
PMU_A53_L2_PWR_SWITCH_INT_EN,
PMU_A53_L3_PWR_SWITCH_INT_EN,
PMU_A72_B0_PWR_SWITCH_INT_EN,
PMU_A72_B1_PWR_SWITCH_INT_EN,
PMU_SCU_L_PWR_SWITCH_INT_EN,
PMU_SCU_B_PWR_SWITCH_INT_EN,
PMU_TCPD0_PWR_SWITCH_INT_EN,
PMU_TCPD1_PWR_SWITCH_INT_EN,
PMU_CCI_PWR_SWITCH_INT_EN,
PMU_PERILP_PWR_SWITCH_INT_EN,
PMU_PERIHP_PWR_SWITCH_INT_EN,
PMU_CENTER_PWR_SWITCH_INT_EN,
PMU_VIO_PWR_SWITCH_INT_EN,
PMU_GPU_PWR_SWITCH_INT_EN,
PMU_VCODEC_PWR_SWITCH_INT_EN,
PMU_VDU_PWR_SWITCH_INT_EN,
PMU_RGA_PWR_SWITCH_INT_EN,
PMU_IEP_PWR_SWITCH_INT_EN,
PMU_VO_PWR_SWITCH_INT_EN,
PMU_ISP0_PWR_SWITCH_INT_EN = 22,
PMU_ISP1_PWR_SWITCH_INT_EN,
PMU_HDCP_PWR_SWITCH_INT_EN,
PMU_GMAC_PWR_SWITCH_INT_EN,
PMU_EMMC_PWR_SWITCH_INT_EN,
PMU_USB3_PWR_SWITCH_INT_EN,
PMU_EDP_PWR_SWITCH_INT_EN,
PMU_GIC_PWR_SWITCH_INT_EN,
PMU_SD_PWR_SWITCH_INT_EN,
PMU_SDIOAUDIO_PWR_SWITCH_INT_EN,
};
enum pmu_wkup_status {
PMU_WKUP_BY_CLSTER_L_INT = 0,
PMU_WKUP_BY_CLSTER_b_INT,
PMU_WKUP_BY_GPIO_INT,
PMU_WKUP_BY_SDIO_DET,
PMU_WKUP_BY_SDMMC_DET,
PMU_WKUP_BY_TIMER = 6,
PMU_WKUP_BY_USBDEV_DET,
PMU_WKUP_BY_M0_SFT,
PMU_WKUP_BY_M0_WDT_INT,
PMU_WKUP_BY_TIMEOUT,
PMU_WKUP_BY_PWM,
PMU_WKUP_BY_PCIE = 13,
};
enum pmu_bus_clr {
PMU_CLR_GPU = 0,
PMU_CLR_PERILP,
PMU_CLR_PERIHP,
PMU_CLR_VCODEC,
PMU_CLR_VDU,
PMU_CLR_RGA,
PMU_CLR_IEP,
PMU_CLR_VOPB,
PMU_CLR_VOPL,
PMU_CLR_ISP0,
PMU_CLR_ISP1,
PMU_CLR_HDCP,
PMU_CLR_USB3,
PMU_CLR_PERILPM0,
PMU_CLR_CENTER,
PMU_CLR_CCIM1,
PMU_CLR_CCIM0,
PMU_CLR_VIO,
PMU_CLR_MSCH0,
PMU_CLR_MSCH1,
PMU_CLR_ALIVE,
PMU_CLR_PMU,
PMU_CLR_EDP,
PMU_CLR_GMAC,
PMU_CLR_EMMC,
PMU_CLR_CENTER1,
PMU_CLR_PMUM0,
PMU_CLR_GIC,
PMU_CLR_SD,
PMU_CLR_SDIOAUDIO,
};
/* PMU bus idle request register */
enum pmu_bus_idle_req {
PMU_IDLE_REQ_GPU = 0,
PMU_IDLE_REQ_PERILP,
PMU_IDLE_REQ_PERIHP,
PMU_IDLE_REQ_VCODEC,
PMU_IDLE_REQ_VDU,
PMU_IDLE_REQ_RGA,
PMU_IDLE_REQ_IEP,
PMU_IDLE_REQ_VOPB,
PMU_IDLE_REQ_VOPL,
PMU_IDLE_REQ_ISP0,
PMU_IDLE_REQ_ISP1,
PMU_IDLE_REQ_HDCP,
PMU_IDLE_REQ_USB3,
PMU_IDLE_REQ_PERILPM0,
PMU_IDLE_REQ_CENTER,
PMU_IDLE_REQ_CCIM0,
PMU_IDLE_REQ_CCIM1,
PMU_IDLE_REQ_VIO,
PMU_IDLE_REQ_MSCH0,
PMU_IDLE_REQ_MSCH1,
PMU_IDLE_REQ_ALIVE,
PMU_IDLE_REQ_PMU,
PMU_IDLE_REQ_EDP,
PMU_IDLE_REQ_GMAC,
PMU_IDLE_REQ_EMMC,
PMU_IDLE_REQ_CENTER1,
PMU_IDLE_REQ_PMUM0,
PMU_IDLE_REQ_GIC,
PMU_IDLE_REQ_SD,
PMU_IDLE_REQ_SDIOAUDIO,
};
/* pmu bus idle status register */
enum pmu_bus_idle_st {
PMU_IDLE_ST_GPU = 0,
PMU_IDLE_ST_PERILP,
PMU_IDLE_ST_PERIHP,
PMU_IDLE_ST_VCODEC,
PMU_IDLE_ST_VDU,
PMU_IDLE_ST_RGA,
PMU_IDLE_ST_IEP,
PMU_IDLE_ST_VOPB,
PMU_IDLE_ST_VOPL,
PMU_IDLE_ST_ISP0,
PMU_IDLE_ST_ISP1,
PMU_IDLE_ST_HDCP,
PMU_IDLE_ST_USB3,
PMU_IDLE_ST_PERILPM0,
PMU_IDLE_ST_CENTER,
PMU_IDLE_ST_CCIM0,
PMU_IDLE_ST_CCIM1,
PMU_IDLE_ST_VIO,
PMU_IDLE_ST_MSCH0,
PMU_IDLE_ST_MSCH1,
PMU_IDLE_ST_ALIVE,
PMU_IDLE_ST_PMU,
PMU_IDLE_ST_EDP,
PMU_IDLE_ST_GMAC,
PMU_IDLE_ST_EMMC,
PMU_IDLE_ST_CENTER1,
PMU_IDLE_ST_PMUM0,
PMU_IDLE_ST_GIC,
PMU_IDLE_ST_SD,
PMU_IDLE_ST_SDIOAUDIO,
};
enum pmu_bus_idle_ack {
PMU_IDLE_ACK_GPU = 0,
PMU_IDLE_ACK_PERILP,
PMU_IDLE_ACK_PERIHP,
PMU_IDLE_ACK_VCODEC,
PMU_IDLE_ACK_VDU,
PMU_IDLE_ACK_RGA,
PMU_IDLE_ACK_IEP,
PMU_IDLE_ACK_VOPB,
PMU_IDLE_ACK_VOPL,
PMU_IDLE_ACK_ISP0,
PMU_IDLE_ACK_ISP1,
PMU_IDLE_ACK_HDCP,
PMU_IDLE_ACK_USB3,
PMU_IDLE_ACK_PERILPM0,
PMU_IDLE_ACK_CENTER,
PMU_IDLE_ACK_CCIM0,
PMU_IDLE_ACK_CCIM1,
PMU_IDLE_ACK_VIO,
PMU_IDLE_ACK_MSCH0,
PMU_IDLE_ACK_MSCH1,
PMU_IDLE_ACK_ALIVE,
PMU_IDLE_ACK_PMU,
PMU_IDLE_ACK_EDP,
PMU_IDLE_ACK_GMAC,
PMU_IDLE_ACK_EMMC,
PMU_IDLE_ACK_CENTER1,
PMU_IDLE_ACK_PMUM0,
PMU_IDLE_ACK_GIC,
PMU_IDLE_ACK_SD,
PMU_IDLE_ACK_SDIOAUDIO,
};
enum pmu_cci500_con {
PMU_PREQ_CCI500_CFG_SW = 0,
PMU_CLR_PREQ_CCI500_HW,
PMU_PSTATE_CCI500_0,
PMU_PSTATE_CCI500_1,
PMU_PSTATE_CCI500_2,
PMU_QREQ_CCI500_CFG_SW,
PMU_CLR_QREQ_CCI500_HW,
PMU_QGATING_CCI500_CFG,
PMU_PREQ_CCI500_CFG_SW_WMSK = 16,
PMU_CLR_PREQ_CCI500_HW_WMSK,
PMU_PSTATE_CCI500_0_WMSK,
PMU_PSTATE_CCI500_1_WMSK,
PMU_PSTATE_CCI500_2_WMSK,
PMU_QREQ_CCI500_CFG_SW_WMSK,
PMU_CLR_QREQ_CCI500_HW_WMSK,
PMU_QGATING_CCI500_CFG_WMSK,
};
enum pmu_adb400_con {
PMU_PWRDWN_REQ_CXCS_SW = 0,
PMU_PWRDWN_REQ_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_B_SW,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW,
PMU_CLR_CXCS_HW = 8,
PMU_CLR_CORE_L_HW,
PMU_CLR_CORE_L_2GIC_HW,
PMU_CLR_GIC2_CORE_L_HW,
PMU_CLR_CORE_B_HW,
PMU_CLR_CORE_B_2GIC_HW,
PMU_CLR_GIC2_CORE_B_HW,
PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16,
PMU_PWRDWN_REQ_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK,
PMU_CLR_CXCS_HW_WMSK = 24,
PMU_CLR_CORE_L_HW_WMSK,
PMU_CLR_CORE_L_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_L_HW_WMSK,
PMU_CLR_CORE_B_HW_WMSK,
PMU_CLR_CORE_B_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_B_HW_WMSK,
};
enum pmu_adb400_st {
PMU_PWRDWN_REQ_CXCS_SW_ST = 0,
PMU_PWRDWN_REQ_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_B_SW_ST,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST,
PMU_CLR_CXCS_HW_ST = 8,
PMU_CLR_CORE_L_HW_ST,
PMU_CLR_CORE_L_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_L_HW_ST,
PMU_CLR_CORE_B_HW_ST,
PMU_CLR_CORE_B_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_B_HW_ST,
};
enum pmu_pwrdn_con1 {
PMU_VD_SCU_L_PWRDN_EN = 0,
PMU_VD_SCU_B_PWRDN_EN,
PMU_VD_CENTER_PWRDN_EN,
};
enum pmu_core_pwr_st {
L2_FLUSHDONE_CLUSTER_L = 0,
STANDBY_BY_WFIL2_CLUSTER_L,
L2_FLUSHDONE_CLUSTER_B = 10,
STANDBY_BY_WFIL2_CLUSTER_B,
};
/* Specific features required */
#define AP_PWROFF 0x0a

173
plat/rockchip/rk3399/drivers/secure/secure.c Normal file
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@ -0,0 +1,173 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <assert.h>
#include <debug.h>
#include <delay_timer.h>
#include <plat_private.h>
#include <secure.h>
#include <soc.h>
static void sgrf_ddr_rgn_global_bypass(uint32_t bypass)
{
if (bypass)
/* set bypass (non-secure regions) for whole ddr regions */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
SGRF_DDR_RGN_BYPS);
else
/* cancel bypass for whole ddr regions */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
SGRF_DDR_RGN_NO_BYPS);
}
/**
* There are 8 + 1 regions for DDR secure control:
* DDR_RGN_0 ~ DDR_RGN_7: Per DDR_RGNs grain size is 1MB
* DDR_RGN_X - the memories of exclude DDR_RGN_0 ~ DDR_RGN_7
*
* DDR_RGN_0 - start address of the RGN0
* DDR_RGN_8 - end address of the RGN0
* DDR_RGN_1 - start address of the RGN1
* DDR_RGN_9 - end address of the RGN1
* ...
* DDR_RGN_7 - start address of the RGN7
* DDR_RGN_15 - end address of the RGN7
* DDR_RGN_16 - bit 0 ~ 7 is bitmap for RGN0~7 secure,0: disable, 1: enable
* bit 8 is setting for RGNx, the rest of the memory and region
* which excludes RGN0~7, 0: disable, 1: enable
* bit 9, the global secure configuration via bypass, 0: disable
* bypass, 1: enable bypass
*
* @rgn - the DDR regions 0 ~ 7 which are can be configured.
* The @st_mb and @ed_mb indicate the start and end addresses for which to set
* the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
* address range 0x0 ~ 0xfffff is secure.
*
* For example, if we would like to set the range [0, 32MB) is security via
* DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
*/
static void sgrf_ddr_rgn_config(uint32_t rgn,
uintptr_t st, uintptr_t ed)
{
uintptr_t st_mb, ed_mb;
assert(rgn <= 7);
assert(st < ed);
/* check aligned 1MB */
assert(st % SIZE_M(1) == 0);
assert(ed % SIZE_M(1) == 0);
st_mb = st / SIZE_M(1);
ed_mb = ed / SIZE_M(1);
/* set ddr region addr start */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn),
BITS_WITH_WMASK(st_mb, SGRF_DDR_RGN_0_16_WMSK, 0));
/* set ddr region addr end */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(rgn + 8),
BITS_WITH_WMASK((ed_mb - 1), SGRF_DDR_RGN_0_16_WMSK, 0));
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
BIT_WITH_WMSK(rgn));
}
void secure_watchdog_disable(void)
{
/**
* Disable CA53 and CM0 wdt pclk
* BIT[8]: ca53 wdt pclk, 0: enable 1: disable
* BIT[10]: cm0 wdt pclk, 0: enable 1: disable
*/
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
BIT_WITH_WMSK(PCLK_WDT_CA53_GATE_SHIFT) |
BIT_WITH_WMSK(PCLK_WDT_CM0_GATE_SHIFT));
}
void secure_watchdog_enable(void)
{
/**
* Enable CA53 and CM0 wdt pclk
* BIT[8]: ca53 wdt pclk, 0: enable 1: disable
* BIT[10]: cm0 wdt pclk, 0: enable 1: disable
*/
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3),
WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) |
WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT));
}
void secure_timer_init(void)
{
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
/* auto reload & enable the timer */
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
TIMER_EN | TIMER_FMODE);
}
void secure_sgrf_init(void)
{
/* security config for master */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5),
REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6),
REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7),
REG_SOC_WMSK | SGRF_SOC_ALLMST_NS);
/* security config for slave */
mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0),
SGRF_PMU_SLV_S_CFGED |
SGRF_PMU_SLV_CRYPTO1_NS);
mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1),
SGRF_SLV_S_WMSK | SGRF_PMUSRAM_S);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4),
SGRF_SLV_S_WMSK | SGRF_INTSRAM_S);
}
void secure_sgrf_ddr_rgn_init(void)
{
sgrf_ddr_rgn_config(0, TZRAM_BASE, TZRAM_SIZE);
sgrf_ddr_rgn_global_bypass(0);
}

128
plat/rockchip/rk3399/drivers/secure/secure.h Normal file
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@ -0,0 +1,128 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__
#define __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__
/**************************************************
* sgrf reg, offset
**************************************************/
#define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4)
#define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4)
#define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4)
#define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\
(n < 8 ? SGRF_SOC_CON3_7(n) :\
SGRF_SOC_CON8_15(n)))
#define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4)
#define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4)
#define SGRF_DDRRGN_CON0_16(n) ((n) * 4)
#define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4)
/* All of master in ns */
#define SGRF_SOC_ALLMST_NS 0xffff
/* security config for slave */
#define SGRF_SLV_S_WMSK 0xffff0000
#define SGRF_SLV_S_ALL_NS 0x0
/* security config pmu slave ip */
/* All of slaves is ns */
#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0)
/* slaves secure attr is configed */
#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0)
#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1)
#define SGRF_PMUSRAM_S BIT(8)
#define SGRF_INTSRAM_S BIT(13)
/* ddr region */
#define SGRF_DDR_RGN_0_16_WMSK 0x0fff /* DDR RGN 0~16 size mask */
#define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */
#define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */
/* All security of the DDR RGNs are bypass */
#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9)
/* All security of the DDR RGNs are not bypass */
#define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(9)
/* The MST access the ddr rgn n with secure attribution */
#define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n))
/* bits[16:8]*/
#define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8)
#define SGRF_PMU_CON0 0x0c100
#define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4)
/**************************************************
* secure timer
**************************************************/
/* chanal0~5 */
#define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
/* chanal6~11 */
#define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n))
/* low 32 bits */
#define TIMER_END_COUNT0 0x00
/* high 32 bits */
#define TIMER_END_COUNT1 0x04
#define TIMER_CURRENT_VALUE0 0x08
#define TIMER_CURRENT_VALUE1 0x0C
/* low 32 bits */
#define TIMER_INIT_COUNT0 0x10
/* high 32 bits */
#define TIMER_INIT_COUNT1 0x14
#define TIMER_INTSTATUS 0x18
#define TIMER_CONTROL_REG 0x1c
#define TIMER_EN 0x1
#define TIMER_FMODE (0x0 << 1)
#define TIMER_RMODE (0x1 << 1)
/**************************************************
* secure WDT
**************************************************/
#define PCLK_WDT_CA53_GATE_SHIFT 8
#define PCLK_WDT_CM0_GATE_SHIFT 10
/* export secure operating APIs */
void secure_watchdog_disable(void);
void secure_watchdog_enable(void);
void secure_timer_init(void);
void secure_sgrf_init(void);
void secure_sgrf_ddr_rgn_init(void);
#endif /* __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ */

186
plat/rockchip/rk3399/drivers/soc/soc.c
View File

@ -29,19 +29,22 @@
*/
#include <arch_helpers.h>
#include <assert.h>
#include <debug.h>
#include <delay_timer.h>
#include <dfs.h>
#include <dram.h>
#include <mmio.h>
#include <m0_ctl.h>
#include <platform_def.h>
#include <plat_private.h>
#include <dram.h>
#include <rk3399_def.h>
#include <rk3399m0.h>
#include <secure.h>
#include <soc.h>
/* Table of regions to map using the MMU. */
const mmap_region_t plat_rk_mmap[] = {
MAP_REGION_FLAT(RK3399_DEV_RNG0_BASE, RK3399_DEV_RNG0_SIZE,
MAP_REGION_FLAT(DEV_RNG0_BASE, DEV_RNG0_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
MT_MEMORY | MT_RW | MT_SECURE),
@ -61,158 +64,8 @@ const unsigned char rockchip_power_domain_tree_desc[] = {
PLATFORM_CLUSTER1_CORE_COUNT
};
void secure_timer_init(void)
{
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0);
/* auto reload & enable the timer */
mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG,
TIMER_EN | TIMER_FMODE);
}
void sgrf_init(void)
{
/* security config for master */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5),
SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6),
SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7),
SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS);
/* security config for slave */
mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0),
SGRF_PMU_SLV_S_CFGED |
SGRF_PMU_SLV_CRYPTO1_NS);
mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1),
SGRF_PMU_SLV_CON1_CFG);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4),
SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS);
/* security config for ddr memery */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16),
SGRF_DDR_RGN_BYPS);
}
static void dma_secure_cfg(uint32_t secure)
{
if (secure) {
/* rgn0 secure for dmac0 and dmac1 */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22),
SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */
SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */
);
/* set dmac0 boot, under secure state */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10),
SGRF_DMAC_CFG_S);
/* dmac0 soft reset */
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC0_RST);
udelay(5);
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC0_RST_RLS);
/* set dmac1 boot, under secure state */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14),
SGRF_DMAC_CFG_S);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15),
SGRF_DMAC_CFG_S);
/* dmac1 soft reset */
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC1_RST);
udelay(5);
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC1_RST_RLS);
} else {
/* rgn non-secure for dmac0 and dmac1 */
mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22),
DMAC1_RGN_NS | DMAC0_RGN_NS);
/* set dmac0 boot, under non-secure state */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8),
DMAC0_BOOT_CFG_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9),
DMAC0_BOOT_PERIPH_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10),
DMAC0_BOOT_ADDR_NS);
/* dmac0 soft reset */
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC0_RST);
udelay(5);
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC0_RST_RLS);
/* set dmac1 boot, under non-secure state */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11),
DMAC1_BOOT_CFG_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12),
DMAC1_BOOT_PERIPH_L_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13),
DMAC1_BOOT_ADDR_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14),
DMAC1_BOOT_PERIPH_H_NS);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15),
DMAC1_BOOT_IRQ_NS);
/* dmac1 soft reset */
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC1_RST);
udelay(5);
mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10),
CRU_DMAC1_RST_RLS);
}
}
/* pll suspend */
struct deepsleep_data_s slp_data;
void secure_watchdog_disable(void)
{
slp_data.sgrf_con[3] = mmio_read_32(SGRF_BASE + SGRF_SOC_CON3_7(3));
/* disable CA53 wdt pclk */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
BITS_WITH_WMASK(WDT_CA53_DIS, WDT_CA53_1BIT_MASK,
PCLK_WDT_CA53_GATE_SHIFT));
/* disable CM0 wdt pclk */
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
BITS_WITH_WMASK(WDT_CM0_DIS, WDT_CM0_1BIT_MASK,
PCLK_WDT_CM0_GATE_SHIFT));
}
void secure_watchdog_restore(void)
{
mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(3),
slp_data.sgrf_con[3] |
WMSK_BIT(PCLK_WDT_CA53_GATE_SHIFT) |
WMSK_BIT(PCLK_WDT_CM0_GATE_SHIFT));
}
/* sleep data for pll suspend */
static struct deepsleep_data_s slp_data;
static void set_pll_slow_mode(uint32_t pll_id)
{
@ -433,7 +286,7 @@ void soc_global_soft_reset_init(void)
CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK);
}
void __dead2 soc_global_soft_reset(void)
void __dead2 soc_global_soft_reset(void)
{
set_pll_slow_mode(VPLL_ID);
set_pll_slow_mode(NPLL_ID);
@ -455,27 +308,14 @@ void __dead2 soc_global_soft_reset(void)
;
}
static void soc_m0_init(void)
{
/* secure config for pmu M0 */
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(0), WMSK_BIT(7));
/* set the execute address for M0 */
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(3),
BITS_WITH_WMASK((M0_BINCODE_BASE >> 12) & 0xffff,
0xffff, 0));
mmio_write_32(SGRF_BASE + SGRF_PMU_CON(7),
BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf,
0xf, 0));
}
void plat_rockchip_soc_init(void)
{
secure_timer_init();
dma_secure_cfg(0);
sgrf_init();
secure_sgrf_init();
secure_sgrf_ddr_rgn_init();
soc_global_soft_reset_init();
plat_rockchip_gpio_init();
soc_m0_init();
m0_init();
dram_init();
dram_dfs_init();
}

129
plat/rockchip/rk3399/drivers/soc/soc.h
View File

@ -75,7 +75,6 @@
#define REG_SOC_WMSK 0xffff0000
#define CLK_GATE_MASK 0x01
#define SGRF_SOC_COUNT 0x17
#define PMUCRU_GATE_COUNT 0x03
#define CRU_GATE_COUNT 0x23
#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4)
@ -108,13 +107,20 @@ enum glb_sft_reset {
PMU_RST_NOT_BY_SFT = BIT(3),
};
struct pll_div {
uint32_t mhz;
uint32_t refdiv;
uint32_t fbdiv;
uint32_t postdiv1;
uint32_t postdiv2;
uint32_t frac;
uint32_t freq;
};
struct deepsleep_data_s {
uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT];
uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT];
uint32_t cru_clksel_con[CRU_CLKSEL_COUNT];
uint32_t cru_gate_con[CRU_GATE_COUNT];
uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
uint32_t sgrf_con[SGRF_SOC_COUNT];
};
/**************************************************
@ -146,50 +152,6 @@ struct deepsleep_data_s {
#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000))
#define CYCL_32K_CNT_MS(ms) (ms * 32)
/**************************************************
* secure timer
**************************************************/
/* chanal0~5 */
#define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
/* chanal6~11 */
#define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n))
/* low 32 bits */
#define TIMER_END_COUNT0 0x00
/* high 32 bits */
#define TIMER_END_COUNT1 0x04
#define TIMER_CURRENT_VALUE0 0x08
#define TIMER_CURRENT_VALUE1 0x0C
/* low 32 bits */
#define TIMER_INIT_COUNT0 0x10
/* high 32 bits */
#define TIMER_INIT_COUNT1 0x14
#define TIMER_INTSTATUS 0x18
#define TIMER_CONTROL_REG 0x1c
#define TIMER_EN 0x1
#define TIMER_FMODE (0x0 << 1)
#define TIMER_RMODE (0x1 << 1)
/**************************************************
* secure WDT
**************************************************/
#define WDT_CM0_EN 0x0
#define WDT_CM0_DIS 0x1
#define WDT_CA53_EN 0x0
#define WDT_CA53_DIS 0x1
#define PCLK_WDT_CA53_GATE_SHIFT 8
#define PCLK_WDT_CM0_GATE_SHIFT 10
#define WDT_CA53_1BIT_MASK 0x1
#define WDT_CM0_1BIT_MASK 0x1
/**************************************************
* cru reg, offset
**************************************************/
@ -231,63 +193,6 @@ struct deepsleep_data_s {
#define PCLK_GPIO0_GATE_SHIFT 3
#define PCLK_GPIO1_GATE_SHIFT 4
/**************************************************
* sgrf reg, offset
**************************************************/
#define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4)
#define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4)
#define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4)
#define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4)
#define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4)
#define SGRF_DDRRGN_CON0_16(n) ((n) * 4)
#define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4)
/* security config for master */
#define SGRF_SOC_CON_WMSK 0xffff0000
/* All of master in ns */
#define SGRF_SOC_ALLMST_NS 0xffff
/* security config for slave */
#define SGRF_SLV_S_WMSK 0xffff0000
#define SGRF_SLV_S_ALL_NS 0x0
/* security config pmu slave ip */
/* All of slaves is ns */
#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0)
/* slaves secure attr is configed */
#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0)
#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1)
#define SGRF_PMUSRAM_S BIT(8)
#define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \
SGRF_PMUSRAM_S)
/* ddr region */
#define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */
#define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */
#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */
/* The MST access the ddr rgn n with secure attribution */
#define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n))
/* bits[16:8]*/
#define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8)
/* dmac to periph s or ns*/
#define SGRF_DMAC_CFG_S 0xffff0000
#define DMAC1_RGN_NS 0xff000000
#define DMAC0_RGN_NS 0x00ff0000
#define DMAC0_BOOT_CFG_NS 0xfffffff8
#define DMAC0_BOOT_PERIPH_NS 0xffff0fff
#define DMAC0_BOOT_ADDR_NS 0xffff0000
#define DMAC1_BOOT_CFG_NS 0xffff0008
#define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff
#define DMAC1_BOOT_ADDR_NS 0xffff0000
#define DMAC1_BOOT_PERIPH_H_NS 0xffffffff
#define DMAC1_BOOT_IRQ_NS 0xffffffff
#define CPU_BOOT_ADDR_WMASK 0xffff0000
#define CPU_BOOT_ADDR_ALIGN 16
@ -312,17 +217,13 @@ struct deepsleep_data_s {
#define GRF_DDRC0_CON1 0xe384
#define GRF_DDRC1_CON0 0xe388
#define GRF_DDRC1_CON1 0xe38c
#define GRF_SOC_CON_BASE 0xe200
#define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4)
#define PMUCRU_CLKSEL_CON0 0x0080
#define PMUCRU_CLKGATE_CON2 0x0108
#define PMUCRU_SOFTRST_CON0 0x0110
#define PMUCRU_GATEDIS_CON0 0x0130
#define SGRF_SOC_CON6 0x0e018
#define SGRF_PERILP_CON0 0x08100
#define SGRF_PERILP_CON(n) (SGRF_PERILP_CON0 + (n) * 4)
#define SGRF_PMU_CON0 0x0c100
#define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4)
#define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4)
/*
@ -346,10 +247,8 @@ static inline void pmu_sgrf_rst_hld(void)
CRU_PMU_SGRF_RST_HOLD);
}
/* funciton*/
/* export related and operating SoC APIs */
void __dead2 soc_global_soft_reset(void);
void secure_watchdog_disable();
void secure_watchdog_restore();
void disable_dvfs_plls(void);
void disable_nodvfs_plls(void);
void enable_dvfs_plls(void);
@ -360,5 +259,5 @@ void restore_dpll(void);
void clk_gate_con_save(void);
void clk_gate_con_disable(void);
void clk_gate_con_restore(void);
void sgrf_init(void);
#endif /* __SOC_H__ */

43
plat/rockchip/rk3399/include/addressmap.h Normal file
View File

@ -0,0 +1,43 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__
#define __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__
#include <addressmap_shared.h>
/* Registers base address */
#define MMIO_BASE 0xF8000000
/* Aggregate of all devices in the first GB */
#define DEV_RNG0_BASE MMIO_BASE
#define DEV_RNG0_SIZE SIZE_M(125)
#endif /* __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__ */

19
plat/rockchip/rk3399/include/platform_def.h
View File

@ -32,6 +32,7 @@
#define __PLATFORM_DEF_H__
#include <arch.h>
#include <bl31_param.h>
#include <common_def.h>
#include <rk3399_def.h>
@ -88,22 +89,6 @@
*/
#define PLAT_MAX_OFF_STATE 2
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
/* TF txet, ro, rw, Size: 512KB */
#define TZRAM_BASE (0x0)
#define TZRAM_SIZE (0x80000)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
/*
* Put BL3-1 at the top of the Trusted RAM
*/
#define BL31_BASE (TZRAM_BASE + 0x10000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
@ -138,7 +123,7 @@
#define PLAT_RK_G1S_IRQS RK3399_G1S_IRQS
#define PLAT_RK_G0_IRQS RK3399_G0_IRQS
#define PLAT_RK_UART_BASE RK3399_UART2_BASE
#define PLAT_RK_UART_BASE UART2_BASE
#define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK
#define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE

122
plat/rockchip/rk3399/include/shared/addressmap_shared.h Normal file
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@ -0,0 +1,122 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__
#define __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__
#define SIZE_K(n) ((n) * 1024)
#define SIZE_M(n) ((n) * 1024 * 1024)
/*
* The parts of the shared defined registers address with AP and M0,
* let's note and mark the previous defines like this:
*/
#define GIC500_BASE (MMIO_BASE + 0x06E00000)
#define UART0_BASE (MMIO_BASE + 0x07180000)
#define UART1_BASE (MMIO_BASE + 0x07190000)
#define UART2_BASE (MMIO_BASE + 0x071A0000)
#define UART3_BASE (MMIO_BASE + 0x071B0000)
#define PMU_BASE (MMIO_BASE + 0x07310000)
#define PMUGRF_BASE (MMIO_BASE + 0x07320000)
#define SGRF_BASE (MMIO_BASE + 0x07330000)
#define PMUSRAM_BASE (MMIO_BASE + 0x073B0000)
#define PWM_BASE (MMIO_BASE + 0x07420000)
#define CIC_BASE (MMIO_BASE + 0x07620000)
#define PD_BUS0_BASE (MMIO_BASE + 0x07650000)
#define DCF_BASE (MMIO_BASE + 0x076A0000)
#define GPIO0_BASE (MMIO_BASE + 0x07720000)
#define GPIO1_BASE (MMIO_BASE + 0x07730000)
#define PMUCRU_BASE (MMIO_BASE + 0x07750000)
#define CRU_BASE (MMIO_BASE + 0x07760000)
#define GRF_BASE (MMIO_BASE + 0x07770000)
#define GPIO2_BASE (MMIO_BASE + 0x07780000)
#define GPIO3_BASE (MMIO_BASE + 0x07788000)
#define GPIO4_BASE (MMIO_BASE + 0x07790000)
#define STIME_BASE (MMIO_BASE + 0x07860000)
#define SRAM_BASE (MMIO_BASE + 0x078C0000)
#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x07A50000)
#define DDRC0_BASE (MMIO_BASE + 0x07A80000)
#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x07A84000)
#define DDRC1_BASE (MMIO_BASE + 0x07A88000)
#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x07A8C000)
#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x07A90000)
#define CCI500_BASE (MMIO_BASE + 0x07B00000)
#define COLD_BOOT_BASE (MMIO_BASE + 0x07FF0000)
/* Registers size */
#define GIC500_SIZE SIZE_M(2)
#define UART0_SIZE SIZE_K(64)
#define UART1_SIZE SIZE_K(64)
#define UART2_SIZE SIZE_K(64)
#define UART3_SIZE SIZE_K(64)
#define PMU_SIZE SIZE_K(64)
#define PMUGRF_SIZE SIZE_K(64)
#define SGRF_SIZE SIZE_K(64)
#define PMUSRAM_SIZE SIZE_K(64)
#define PMUSRAM_RSIZE SIZE_K(8)
#define PWM_SIZE SIZE_K(64)
#define CIC_SIZE SIZE_K(4)
#define DCF_SIZE SIZE_K(4)
#define GPIO0_SIZE SIZE_K(64)
#define GPIO1_SIZE SIZE_K(64)
#define PMUCRU_SIZE SIZE_K(64)
#define CRU_SIZE SIZE_K(64)
#define GRF_SIZE SIZE_K(64)
#define GPIO2_SIZE SIZE_K(32)
#define GPIO3_SIZE SIZE_K(32)
#define GPIO4_SIZE SIZE_K(32)
#define STIME_SIZE SIZE_K(64)
#define SRAM_SIZE SIZE_K(192)
#define SERVICE_NOC_0_SIZE SIZE_K(192)
#define DDRC0_SIZE SIZE_K(32)
#define SERVICE_NOC_1_SIZE SIZE_K(16)
#define DDRC1_SIZE SIZE_K(32)
#define SERVICE_NOC_2_SIZE SIZE_K(16)
#define SERVICE_NOC_3_SIZE SIZE_K(448)
#define CCI500_SIZE SIZE_M(1)
#define PD_BUS0_SIZE SIZE_K(448)
/* DDR Registers address */
#define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000)
#define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4)
#define PI_OFFSET 0x800
#define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET)
#define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4)
#define PHY_OFFSET 0x2000
#define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET)
#define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4)
#define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000)
#endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ */

50
plat/rockchip/rk3399/include/shared/bl31_param.h Normal file
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@ -0,0 +1,50 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLAT_ROCKCHIP_RK3399_INCLUDE_SHARED_BL31_PARAM_H__
#define __PLAT_ROCKCHIP_RK3399_INCLUDE_SHARED_BL31_PARAM_H__
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
/* TF text, ro, rw, Size: 1MB */
#define TZRAM_BASE (0x0)
#define TZRAM_SIZE (0x100000)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
/*
* Put BL3-1 at the top of the Trusted RAM
*/
#define BL31_BASE (TZRAM_BASE + 0x1000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
#endif /*__PLAT_ROCKCHIP_RK3399_INCLUDE_SHARED_BL31_PARAM_H__*/

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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DRAM_REGS_H__
#define __DRAM_REGS_H__
#define CTL_REG_NUM 332
#define PHY_REG_NUM 959
#define PI_REG_NUM 200
#define MSCH_ID_COREID 0x0
#define MSCH_ID_REVISIONID 0x4
#define MSCH_DEVICECONF 0x8
#define MSCH_DEVICESIZE 0xc
#define MSCH_DDRTIMINGA0 0x10
#define MSCH_DDRTIMINGB0 0x14
#define MSCH_DDRTIMINGC0 0x18
#define MSCH_DEVTODEV0 0x1c
#define MSCH_DDRMODE 0x110
#define MSCH_AGINGX0 0x1000
#define CIC_CTRL0 0x0
#define CIC_CTRL1 0x4
#define CIC_IDLE_TH 0x8
#define CIC_CG_WAIT_TH 0xc
#define CIC_STATUS0 0x10
#define CIC_STATUS1 0x14
#define CIC_CTRL2 0x18
#define CIC_CTRL3 0x1c
#define CIC_CTRL4 0x20
/* DENALI_CTL_00 */
#define START 1
/* DENALI_CTL_68 */
#define PWRUP_SREFRESH_EXIT (1 << 16)
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
#define PHY_DRV_ODT_Hi_Z 0x0
#define PHY_DRV_ODT_240 0x1
#define PHY_DRV_ODT_120 0x8
#define PHY_DRV_ODT_80 0x9
#define PHY_DRV_ODT_60 0xc
#define PHY_DRV_ODT_48 0xd
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
/*
* sys_reg bitfield struct
* [31] row_3_4_ch1
* [30] row_3_4_ch0
* [29:28] chinfo
* [27] rank_ch1
* [26:25] col_ch1
* [24] bk_ch1
* [23:22] cs0_row_ch1
* [21:20] cs1_row_ch1
* [19:18] bw_ch1
* [17:16] dbw_ch1;
* [15:13] ddrtype
* [12] channelnum
* [11] rank_ch0
* [10:9] col_ch0
* [8] bk_ch0
* [7:6] cs0_row_ch0
* [5:4] cs1_row_ch0
* [3:2] bw_ch0
* [1:0] dbw_ch0
*/
#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1)
#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
#define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1)
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7)
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1))
#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16))
#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16))
#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16))
#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16))
#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16))
#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16))
#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16))
#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3))
#define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \
(0x1f<<(10+16))|((n)<<10))
#endif /* __DRAM_REGS_H__ */

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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __M0_PARAM_H__
#define __M0_PARAM_H__
#ifndef __LINKER__
enum {
M0_FUNC_SUSPEND = 0,
M0_FUNC_DRAM = 1,
};
#endif /* __LINKER__ */
#define PARAM_ADDR 0xc0
#define PARAM_M0_FUNC 0x00
#define PARAM_DRAM_FREQ 0x04
#define PARAM_DPLL_CON0 0x08
#define PARAM_DPLL_CON1 0x0c
#define PARAM_DPLL_CON2 0x10
#define PARAM_DPLL_CON3 0x14
#define PARAM_DPLL_CON4 0x18
#define PARAM_DPLL_CON5 0x1c
#define PARAM_FREQ_SELECT 0x20
#define PARAM_M0_DONE 0x24
#define PARAM_M0_SIZE 0x28
#define M0_DONE_FLAG 0xf59ec39a
#endif /*__M0_PARAM_H__*/

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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__
#define __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__
/* CRU */
#define CRU_DPLL_CON0 0x40
#define CRU_DPLL_CON1 0x44
#define CRU_DPLL_CON2 0x48
#define CRU_DPLL_CON3 0x4c
#define CRU_DPLL_CON4 0x50
#define CRU_DPLL_CON5 0x54
/* CRU_PLL_CON3 */
#define PLL_SLOW_MODE 0
#define PLL_NORMAL_MODE 1
#define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8))
#define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0))
/* PMU CRU */
#define PMU_CRU_GATEDIS_CON0 0x130
#endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ */

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/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PMU_BITS_H__
#define __PMU_BITS_H__
enum pmu_powerdomain_id {
PD_CPUL0 = 0,
PD_CPUL1,
PD_CPUL2,
PD_CPUL3,
PD_CPUB0,
PD_CPUB1,
PD_SCUL,
PD_SCUB,
PD_TCPD0,
PD_TCPD1,
PD_CCI,
PD_PERILP,
PD_PERIHP,
PD_CENTER,
PD_VIO,
PD_GPU,
PD_VCODEC,
PD_VDU,
PD_RGA,
PD_IEP,
PD_VO,
PD_ISP0 = 22,
PD_ISP1,
PD_HDCP,
PD_GMAC,
PD_EMMC,
PD_USB3,
PD_EDP,
PD_GIC,
PD_SD,
PD_SDIOAUDIO,
PD_END
};
enum powerdomain_state {
PMU_POWER_ON = 0,
PMU_POWER_OFF,
};
enum pmu_bus_id {
BUS_ID_GPU = 0,
BUS_ID_PERILP,
BUS_ID_PERIHP,
BUS_ID_VCODEC,
BUS_ID_VDU,
BUS_ID_RGA,
BUS_ID_IEP,
BUS_ID_VOPB,
BUS_ID_VOPL,
BUS_ID_ISP0,
BUS_ID_ISP1,
BUS_ID_HDCP,
BUS_ID_USB3,
BUS_ID_PERILPM0,
BUS_ID_CENTER,
BUS_ID_CCIM0,
BUS_ID_CCIM1,
BUS_ID_VIO,
BUS_ID_MSCH0,
BUS_ID_MSCH1,
BUS_ID_ALIVE,
BUS_ID_PMU,
BUS_ID_EDP,
BUS_ID_GMAC,
BUS_ID_EMMC,
BUS_ID_CENTER1,
BUS_ID_PMUM0,
BUS_ID_GIC,
BUS_ID_SD,
BUS_ID_SDIOAUDIO,
};
enum pmu_bus_state {
BUS_ACTIVE,
BUS_IDLE,
};
/* pmu_cpuapm bit */
enum pmu_cores_pm_by_wfi {
core_pm_en = 0,
core_pm_int_wakeup_en,
core_pm_resv,
core_pm_sft_wakeup_en
};
enum pmu_wkup_cfg0 {
PMU_GPIO0A_POSE_WKUP_EN = 0,
PMU_GPIO0B_POSE_WKUP_EN = 8,
PMU_GPIO0C_POSE_WKUP_EN = 16,
PMU_GPIO0D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg1 {
PMU_GPIO0A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO0B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO0C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO0D_NEGEDGE_WKUP_EN = 24,
};
enum pmu_wkup_cfg2 {
PMU_GPIO1A_POSE_WKUP_EN = 0,
PMU_GPIO1B_POSE_WKUP_EN = 7,
PMU_GPIO1C_POSE_WKUP_EN = 16,
PMU_GPIO1D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg3 {
PMU_GPIO1A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO1B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO1C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO1D_NEGEDGE_WKUP_EN = 24,
};
/* pmu_wkup_cfg4 */
enum pmu_wkup_cfg4 {
PMU_CLUSTER_L_WKUP_EN = 0,
PMU_CLUSTER_B_WKUP_EN,
PMU_GPIO_WKUP_EN,
PMU_SDIO_WKUP_EN,
PMU_SDMMC_WKUP_EN,
PMU_TIMER_WKUP_EN = 6,
PMU_USBDEV_WKUP_EN,
PMU_SFT_WKUP_EN,
PMU_M0_WDT_WKUP_EN,
PMU_TIMEOUT_WKUP_EN,
PMU_PWM_WKUP_EN,
PMU_PCIE_WKUP_EN = 13,
};
enum pmu_pwrdn_con {
PMU_A53_L0_PWRDWN_EN = 0,
PMU_A53_L1_PWRDWN_EN,
PMU_A53_L2_PWRDWN_EN,
PMU_A53_L3_PWRDWN_EN,
PMU_A72_B0_PWRDWN_EN,
PMU_A72_B1_PWRDWN_EN,
PMU_SCU_L_PWRDWN_EN,
PMU_SCU_B_PWRDWN_EN,
PMU_TCPD0_PWRDWN_EN,
PMU_TCPD1_PWRDWN_EN,
PMU_CCI_PWRDWN_EN,
PMU_PERILP_PWRDWN_EN,
PMU_PERIHP_PWRDWN_EN,
PMU_CENTER_PWRDWN_EN,
PMU_VIO_PWRDWN_EN,
PMU_GPU_PWRDWN_EN,
PMU_VCODEC_PWRDWN_EN,
PMU_VDU_PWRDWN_EN,
PMU_RGA_PWRDWN_EN,
PMU_IEP_PWRDWN_EN,
PMU_VO_PWRDWN_EN,
PMU_ISP0_PWRDWN_EN = 22,
PMU_ISP1_PWRDWN_EN,
PMU_HDCP_PWRDWN_EN,
PMU_GMAC_PWRDWN_EN,
PMU_EMMC_PWRDWN_EN,
PMU_USB3_PWRDWN_EN,
PMU_EDP_PWRDWN_EN,
PMU_GIC_PWRDWN_EN,
PMU_SD_PWRDWN_EN,
PMU_SDIOAUDIO_PWRDWN_EN,
};
enum pmu_pwrdn_st {
PMU_A53_L0_PWRDWN_ST = 0,
PMU_A53_L1_PWRDWN_ST,
PMU_A53_L2_PWRDWN_ST,
PMU_A53_L3_PWRDWN_ST,
PMU_A72_B0_PWRDWN_ST,
PMU_A72_B1_PWRDWN_ST,
PMU_SCU_L_PWRDWN_ST,
PMU_SCU_B_PWRDWN_ST,
PMU_TCPD0_PWRDWN_ST,
PMU_TCPD1_PWRDWN_ST,
PMU_CCI_PWRDWN_ST,
PMU_PERILP_PWRDWN_ST,
PMU_PERIHP_PWRDWN_ST,
PMU_CENTER_PWRDWN_ST,
PMU_VIO_PWRDWN_ST,
PMU_GPU_PWRDWN_ST,
PMU_VCODEC_PWRDWN_ST,
PMU_VDU_PWRDWN_ST,
PMU_RGA_PWRDWN_ST,
PMU_IEP_PWRDWN_ST,
PMU_VO_PWRDWN_ST,
PMU_ISP0_PWRDWN_ST = 22,
PMU_ISP1_PWRDWN_ST,
PMU_HDCP_PWRDWN_ST,
PMU_GMAC_PWRDWN_ST,
PMU_EMMC_PWRDWN_ST,
PMU_USB3_PWRDWN_ST,
PMU_EDP_PWRDWN_ST,
PMU_GIC_PWRDWN_ST,
PMU_SD_PWRDWN_ST,
PMU_SDIOAUDIO_PWRDWN_ST,
};
enum pmu_pll_con {
PMU_PLL_PD_CFG = 0,
PMU_SFT_PLL_PD = 8,
};
enum pmu_pwermode_con {
PMU_PWR_MODE_EN = 0,
PMU_WKUP_RST_EN,
PMU_INPUT_CLAMP_EN,
PMU_OSC_DIS,
PMU_ALIVE_USE_LF,
PMU_PMU_USE_LF,
PMU_POWER_OFF_REQ_CFG,
PMU_CHIP_PD_EN,
PMU_PLL_PD_EN,
PMU_CPU0_PD_EN,
PMU_L2_FLUSH_EN,
PMU_L2_IDLE_EN,
PMU_SCU_PD_EN,
PMU_CCI_PD_EN,
PMU_PERILP_PD_EN,
PMU_CENTER_PD_EN,
PMU_SREF0_ENTER_EN,
PMU_DDRC0_GATING_EN,
PMU_DDRIO0_RET_EN,
PMU_DDRIO0_RET_DE_REQ,
PMU_SREF1_ENTER_EN,
PMU_DDRC1_GATING_EN,
PMU_DDRIO1_RET_EN,
PMU_DDRIO1_RET_DE_REQ,
PMU_CLK_CENTER_SRC_GATE_EN = 26,
PMU_CLK_PERILP_SRC_GATE_EN,
PMU_CLK_CORE_SRC_GATE_EN,
PMU_DDRIO_RET_HW_DE_REQ,
PMU_SLP_OUTPUT_CFG,
PMU_MAIN_CLUSTER,
};
enum pmu_sft_con {
PMU_WKUP_SFT = 0,
PMU_INPUT_CLAMP_CFG,
PMU_OSC_DIS_CFG,
PMU_PMU_LF_EN_CFG,
PMU_ALIVE_LF_EN_CFG,
PMU_24M_EN_CFG,
PMU_DBG_PWRUP_L0_CFG,
PMU_WKUP_SFT_M0,
PMU_DDRCTL0_C_SYSREQ_CFG,
PMU_DDR0_IO_RET_CFG,
PMU_DDRCTL1_C_SYSREQ_CFG = 12,
PMU_DDR1_IO_RET_CFG,
DBG_PWRUP_B0_CFG = 15,
DBG_NOPWERDWN_L0_EN,
DBG_NOPWERDWN_L1_EN,
DBG_NOPWERDWN_L2_EN,
DBG_NOPWERDWN_L3_EN,
DBG_PWRUP_REQ_L_EN = 20,
CLUSTER_L_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_L,
ACINACTM_CLUSTER_L_CFG,
DBG_NO_PWERDWN_B0_EN,
DBG_NO_PWERDWN_B1_EN,
DBG_PWRUP_REQ_B_EN = 28,
CLUSTER_B_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_B,
ACINACTM_CLUSTER_B_CFG,
};
enum pmu_int_con {
PMU_PMU_INT_EN = 0,
PMU_PWRMD_WKUP_INT_EN,
PMU_WKUP_GPIO0_NEG_INT_EN,
PMU_WKUP_GPIO0_POS_INT_EN,
PMU_WKUP_GPIO1_NEG_INT_EN,
PMU_WKUP_GPIO1_POS_INT_EN,
};
enum pmu_int_st {
PMU_PWRMD_WKUP_INT_ST = 1,
PMU_WKUP_GPIO0_NEG_INT_ST,
PMU_WKUP_GPIO0_POS_INT_ST,
PMU_WKUP_GPIO1_NEG_INT_ST,
PMU_WKUP_GPIO1_POS_INT_ST,
};
enum pmu_gpio0_pos_int_con {
PMU_GPIO0A_POS_INT_EN = 0,
PMU_GPIO0B_POS_INT_EN = 8,
PMU_GPIO0C_POS_INT_EN = 16,
PMU_GPIO0D_POS_INT_EN = 24,
};
enum pmu_gpio0_neg_int_con {
PMU_GPIO0A_NEG_INT_EN = 0,
PMU_GPIO0B_NEG_INT_EN = 8,
PMU_GPIO0C_NEG_INT_EN = 16,
PMU_GPIO0D_NEG_INT_EN = 24,
};
enum pmu_gpio1_pos_int_con {
PMU_GPIO1A_POS_INT_EN = 0,
PMU_GPIO1B_POS_INT_EN = 8,
PMU_GPIO1C_POS_INT_EN = 16,
PMU_GPIO1D_POS_INT_EN = 24,
};
enum pmu_gpio1_neg_int_con {
PMU_GPIO1A_NEG_INT_EN = 0,
PMU_GPIO1B_NEG_INT_EN = 8,
PMU_GPIO1C_NEG_INT_EN = 16,
PMU_GPIO1D_NEG_INT_EN = 24,
};
enum pmu_gpio0_pos_int_st {
PMU_GPIO0A_POS_INT_ST = 0,
PMU_GPIO0B_POS_INT_ST = 8,
PMU_GPIO0C_POS_INT_ST = 16,
PMU_GPIO0D_POS_INT_ST = 24,
};
enum pmu_gpio0_neg_int_st {
PMU_GPIO0A_NEG_INT_ST = 0,
PMU_GPIO0B_NEG_INT_ST = 8,
PMU_GPIO0C_NEG_INT_ST = 16,
PMU_GPIO0D_NEG_INT_ST = 24,
};
enum pmu_gpio1_pos_int_st {
PMU_GPIO1A_POS_INT_ST = 0,
PMU_GPIO1B_POS_INT_ST = 8,
PMU_GPIO1C_POS_INT_ST = 16,
PMU_GPIO1D_POS_INT_ST = 24,
};
enum pmu_gpio1_neg_int_st {
PMU_GPIO1A_NEG_INT_ST = 0,
PMU_GPIO1B_NEG_INT_ST = 8,
PMU_GPIO1C_NEG_INT_ST = 16,
PMU_GPIO1D_NEG_INT_ST = 24,
};
/* pmu power down configure register 0x0050 */
enum pmu_pwrdn_inten {
PMU_A53_L0_PWR_SWITCH_INT_EN = 0,
PMU_A53_L1_PWR_SWITCH_INT_EN,
PMU_A53_L2_PWR_SWITCH_INT_EN,
PMU_A53_L3_PWR_SWITCH_INT_EN,
PMU_A72_B0_PWR_SWITCH_INT_EN,
PMU_A72_B1_PWR_SWITCH_INT_EN,
PMU_SCU_L_PWR_SWITCH_INT_EN,
PMU_SCU_B_PWR_SWITCH_INT_EN,
PMU_TCPD0_PWR_SWITCH_INT_EN,
PMU_TCPD1_PWR_SWITCH_INT_EN,
PMU_CCI_PWR_SWITCH_INT_EN,
PMU_PERILP_PWR_SWITCH_INT_EN,
PMU_PERIHP_PWR_SWITCH_INT_EN,
PMU_CENTER_PWR_SWITCH_INT_EN,
PMU_VIO_PWR_SWITCH_INT_EN,
PMU_GPU_PWR_SWITCH_INT_EN,
PMU_VCODEC_PWR_SWITCH_INT_EN,
PMU_VDU_PWR_SWITCH_INT_EN,
PMU_RGA_PWR_SWITCH_INT_EN,
PMU_IEP_PWR_SWITCH_INT_EN,
PMU_VO_PWR_SWITCH_INT_EN,
PMU_ISP0_PWR_SWITCH_INT_EN = 22,
PMU_ISP1_PWR_SWITCH_INT_EN,
PMU_HDCP_PWR_SWITCH_INT_EN,
PMU_GMAC_PWR_SWITCH_INT_EN,
PMU_EMMC_PWR_SWITCH_INT_EN,
PMU_USB3_PWR_SWITCH_INT_EN,
PMU_EDP_PWR_SWITCH_INT_EN,
PMU_GIC_PWR_SWITCH_INT_EN,
PMU_SD_PWR_SWITCH_INT_EN,
PMU_SDIOAUDIO_PWR_SWITCH_INT_EN,
};
enum pmu_wkup_status {
PMU_WKUP_BY_CLSTER_L_INT = 0,
PMU_WKUP_BY_CLSTER_b_INT,
PMU_WKUP_BY_GPIO_INT,
PMU_WKUP_BY_SDIO_DET,
PMU_WKUP_BY_SDMMC_DET,
PMU_WKUP_BY_TIMER = 6,
PMU_WKUP_BY_USBDEV_DET,
PMU_WKUP_BY_M0_SFT,
PMU_WKUP_BY_M0_WDT_INT,
PMU_WKUP_BY_TIMEOUT,
PMU_WKUP_BY_PWM,
PMU_WKUP_BY_PCIE = 13,
};
enum pmu_bus_clr {
PMU_CLR_GPU = 0,
PMU_CLR_PERILP,
PMU_CLR_PERIHP,
PMU_CLR_VCODEC,
PMU_CLR_VDU,
PMU_CLR_RGA,
PMU_CLR_IEP,
PMU_CLR_VOPB,
PMU_CLR_VOPL,
PMU_CLR_ISP0,
PMU_CLR_ISP1,
PMU_CLR_HDCP,
PMU_CLR_USB3,
PMU_CLR_PERILPM0,
PMU_CLR_CENTER,
PMU_CLR_CCIM1,
PMU_CLR_CCIM0,
PMU_CLR_VIO,
PMU_CLR_MSCH0,
PMU_CLR_MSCH1,
PMU_CLR_ALIVE,
PMU_CLR_PMU,
PMU_CLR_EDP,
PMU_CLR_GMAC,
PMU_CLR_EMMC,
PMU_CLR_CENTER1,
PMU_CLR_PMUM0,
PMU_CLR_GIC,
PMU_CLR_SD,
PMU_CLR_SDIOAUDIO,
};
/* PMU bus idle request register */
enum pmu_bus_idle_req {
PMU_IDLE_REQ_GPU = 0,
PMU_IDLE_REQ_PERILP,
PMU_IDLE_REQ_PERIHP,
PMU_IDLE_REQ_VCODEC,
PMU_IDLE_REQ_VDU,
PMU_IDLE_REQ_RGA,
PMU_IDLE_REQ_IEP,
PMU_IDLE_REQ_VOPB,
PMU_IDLE_REQ_VOPL,
PMU_IDLE_REQ_ISP0,
PMU_IDLE_REQ_ISP1,
PMU_IDLE_REQ_HDCP,
PMU_IDLE_REQ_USB3,
PMU_IDLE_REQ_PERILPM0,
PMU_IDLE_REQ_CENTER,
PMU_IDLE_REQ_CCIM0,
PMU_IDLE_REQ_CCIM1,
PMU_IDLE_REQ_VIO,
PMU_IDLE_REQ_MSCH0,
PMU_IDLE_REQ_MSCH1,
PMU_IDLE_REQ_ALIVE,
PMU_IDLE_REQ_PMU,
PMU_IDLE_REQ_EDP,
PMU_IDLE_REQ_GMAC,
PMU_IDLE_REQ_EMMC,
PMU_IDLE_REQ_CENTER1,
PMU_IDLE_REQ_PMUM0,
PMU_IDLE_REQ_GIC,
PMU_IDLE_REQ_SD,
PMU_IDLE_REQ_SDIOAUDIO,
};
/* pmu bus idle status register */
enum pmu_bus_idle_st {
PMU_IDLE_ST_GPU = 0,
PMU_IDLE_ST_PERILP,
PMU_IDLE_ST_PERIHP,
PMU_IDLE_ST_VCODEC,
PMU_IDLE_ST_VDU,
PMU_IDLE_ST_RGA,
PMU_IDLE_ST_IEP,
PMU_IDLE_ST_VOPB,
PMU_IDLE_ST_VOPL,
PMU_IDLE_ST_ISP0,
PMU_IDLE_ST_ISP1,
PMU_IDLE_ST_HDCP,
PMU_IDLE_ST_USB3,
PMU_IDLE_ST_PERILPM0,
PMU_IDLE_ST_CENTER,
PMU_IDLE_ST_CCIM0,
PMU_IDLE_ST_CCIM1,
PMU_IDLE_ST_VIO,
PMU_IDLE_ST_MSCH0,
PMU_IDLE_ST_MSCH1,
PMU_IDLE_ST_ALIVE,
PMU_IDLE_ST_PMU,
PMU_IDLE_ST_EDP,
PMU_IDLE_ST_GMAC,
PMU_IDLE_ST_EMMC,
PMU_IDLE_ST_CENTER1,
PMU_IDLE_ST_PMUM0,
PMU_IDLE_ST_GIC,
PMU_IDLE_ST_SD,
PMU_IDLE_ST_SDIOAUDIO,
};
enum pmu_bus_idle_ack {
PMU_IDLE_ACK_GPU = 0,
PMU_IDLE_ACK_PERILP,
PMU_IDLE_ACK_PERIHP,
PMU_IDLE_ACK_VCODEC,
PMU_IDLE_ACK_VDU,
PMU_IDLE_ACK_RGA,
PMU_IDLE_ACK_IEP,
PMU_IDLE_ACK_VOPB,
PMU_IDLE_ACK_VOPL,
PMU_IDLE_ACK_ISP0,
PMU_IDLE_ACK_ISP1,
PMU_IDLE_ACK_HDCP,
PMU_IDLE_ACK_USB3,
PMU_IDLE_ACK_PERILPM0,
PMU_IDLE_ACK_CENTER,
PMU_IDLE_ACK_CCIM0,
PMU_IDLE_ACK_CCIM1,
PMU_IDLE_ACK_VIO,
PMU_IDLE_ACK_MSCH0,
PMU_IDLE_ACK_MSCH1,
PMU_IDLE_ACK_ALIVE,
PMU_IDLE_ACK_PMU,
PMU_IDLE_ACK_EDP,
PMU_IDLE_ACK_GMAC,
PMU_IDLE_ACK_EMMC,
PMU_IDLE_ACK_CENTER1,
PMU_IDLE_ACK_PMUM0,
PMU_IDLE_ACK_GIC,
PMU_IDLE_ACK_SD,
PMU_IDLE_ACK_SDIOAUDIO,
};
enum pmu_cci500_con {
PMU_PREQ_CCI500_CFG_SW = 0,
PMU_CLR_PREQ_CCI500_HW,
PMU_PSTATE_CCI500_0,
PMU_PSTATE_CCI500_1,
PMU_PSTATE_CCI500_2,
PMU_QREQ_CCI500_CFG_SW,
PMU_CLR_QREQ_CCI500_HW,
PMU_QGATING_CCI500_CFG,
PMU_PREQ_CCI500_CFG_SW_WMSK = 16,
PMU_CLR_PREQ_CCI500_HW_WMSK,
PMU_PSTATE_CCI500_0_WMSK,
PMU_PSTATE_CCI500_1_WMSK,
PMU_PSTATE_CCI500_2_WMSK,
PMU_QREQ_CCI500_CFG_SW_WMSK,
PMU_CLR_QREQ_CCI500_HW_WMSK,
PMU_QGATING_CCI500_CFG_WMSK,
};
enum pmu_adb400_con {
PMU_PWRDWN_REQ_CXCS_SW = 0,
PMU_PWRDWN_REQ_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_B_SW,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW,
PMU_CLR_CXCS_HW = 8,
PMU_CLR_CORE_L_HW,
PMU_CLR_CORE_L_2GIC_HW,
PMU_CLR_GIC2_CORE_L_HW,
PMU_CLR_CORE_B_HW,
PMU_CLR_CORE_B_2GIC_HW,
PMU_CLR_GIC2_CORE_B_HW,
PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16,
PMU_PWRDWN_REQ_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK,
PMU_CLR_CXCS_HW_WMSK = 24,
PMU_CLR_CORE_L_HW_WMSK,
PMU_CLR_CORE_L_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_L_HW_WMSK,
PMU_CLR_CORE_B_HW_WMSK,
PMU_CLR_CORE_B_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_B_HW_WMSK,
};
enum pmu_adb400_st {
PMU_PWRDWN_REQ_CXCS_SW_ST = 0,
PMU_PWRDWN_REQ_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_B_SW_ST,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST,
PMU_CLR_CXCS_HW_ST = 8,
PMU_CLR_CORE_L_HW_ST,
PMU_CLR_CORE_L_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_L_HW_ST,
PMU_CLR_CORE_B_HW_ST,
PMU_CLR_CORE_B_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_B_HW_ST,
};
enum pmu_pwrdn_con1 {
PMU_VD_SCU_L_PWRDN_EN = 0,
PMU_VD_SCU_B_PWRDN_EN,
PMU_VD_CENTER_PWRDN_EN,
};
enum pmu_core_pwr_st {
L2_FLUSHDONE_CLUSTER_L = 0,
STANDBY_BY_WFIL2_CLUSTER_L,
L2_FLUSHDONE_CLUSTER_B = 10,
STANDBY_BY_WFIL2_CLUSTER_B,
};
#endif /* __PMU_BITS_H__ */

0
plat/rockchip/rk3399/drivers/pmu/pmu_regs.h → plat/rockchip/rk3399/include/shared/pmu_regs.h
View File

16
plat/rockchip/rk3399/plat_sip_calls.c
View File

@ -44,24 +44,20 @@
#define DRAM_GET_RATE 0x05
#define DRAM_CLR_IRQ 0x06
#define DRAM_SET_PARAM 0x07
#define DRAM_SET_ODT_PD 0x08
uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id)
uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1,
uint64_t id, uint64_t arg2)
{
switch (id) {
case DRAM_INIT:
ddr_dfs_init();
break;
case DRAM_SET_RATE:
return ddr_set_rate((uint32_t)arg0);
case DRAM_ROUND_RATE:
return ddr_round_rate((uint32_t)arg0);
case DRAM_GET_RATE:
return ddr_get_rate();
case DRAM_CLR_IRQ:
clr_dcf_irq();
break;
case DRAM_SET_PARAM:
dts_timing_receive((uint32_t)arg0, (uint32_t)arg1);
case DRAM_SET_ODT_PD:
dram_set_odt_pd(arg0, arg1, arg2);
break;
default:
break;
@ -81,7 +77,7 @@ uint64_t rockchip_plat_sip_handler(uint32_t smc_fid,
{
switch (smc_fid) {
case RK_SIP_DDR_CFG:
SMC_RET1(handle, ddr_smc_handler(x1, x2, x3));
SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4));
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
SMC_RET1(handle, SMC_UNK);

106
plat/rockchip/rk3399/platform.mk
View File

@ -28,63 +28,67 @@
# POSSIBILITY OF SUCH DAMAGE.
#
RK_PLAT := plat/rockchip
RK_PLAT_SOC := ${RK_PLAT}/${PLAT}
RK_PLAT_COMMON := ${RK_PLAT}/common
RK_PLAT := plat/rockchip
RK_PLAT_SOC := ${RK_PLAT}/${PLAT}
RK_PLAT_COMMON := ${RK_PLAT}/common
PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \
-I${RK_PLAT_COMMON}/include/ \
-I${RK_PLAT_COMMON}/pmusram \
-I${RK_PLAT_COMMON}/drivers/pmu/ \
-I${RK_PLAT_SOC}/ \
-I${RK_PLAT_SOC}/drivers/pmu/ \
-I${RK_PLAT_SOC}/drivers/pwm/ \
-I${RK_PLAT_SOC}/drivers/soc/ \
-I${RK_PLAT_SOC}/drivers/dram/ \
-I${RK_PLAT_SOC}/include/ \
PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \
-I${RK_PLAT_COMMON}/include/ \
-I${RK_PLAT_COMMON}/pmusram \
-I${RK_PLAT_COMMON}/drivers/pmu/ \
-I${RK_PLAT_SOC}/ \
-I${RK_PLAT_SOC}/drivers/pmu/ \
-I${RK_PLAT_SOC}/drivers/pwm/ \
-I${RK_PLAT_SOC}/drivers/secure/ \
-I${RK_PLAT_SOC}/drivers/soc/ \
-I${RK_PLAT_SOC}/drivers/dram/ \
-I${RK_PLAT_SOC}/include/ \
-I${RK_PLAT_SOC}/include/shared/ \
RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/v3/gicv3_helpers.c \
plat/common/plat_gicv3.c \
${RK_PLAT}/common/rockchip_gicv3.c
RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v3/gicv3_main.c \
drivers/arm/gic/v3/gicv3_helpers.c \
plat/common/plat_gicv3.c \
${RK_PLAT}/common/rockchip_gicv3.c
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
plat/common/aarch64/plat_common.c \
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
plat/common/aarch64/plat_common.c \
plat/common/plat_psci_common.c
BL31_SOURCES += ${RK_GIC_SOURCES} \
drivers/arm/cci/cci.c \
drivers/console/aarch64/console.S \
drivers/ti/uart/aarch64/16550_console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/gpio/gpio.c \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a72.S \
plat/common/aarch64/platform_mp_stack.S \
${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
${RK_PLAT_COMMON}/bl31_plat_setup.c \
${RK_PLAT_COMMON}/params_setup.c \
${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \
${RK_PLAT_COMMON}/pmusram/pmu_sram.c \
${RK_PLAT_COMMON}/plat_pm.c \
${RK_PLAT_COMMON}/plat_topology.c \
${RK_PLAT_COMMON}/aarch64/platform_common.c \
${RK_PLAT_COMMON}/rockchip_sip_svc.c \
${RK_PLAT_SOC}/plat_sip_calls.c \
${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c \
${RK_PLAT_SOC}/drivers/pwm/pwm.c \
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/drivers/dram/dfs.c \
${RK_PLAT_SOC}/drivers/dram/suspend.c \
${RK_PLAT_SOC}/drivers/dram/dram.c \
${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c
BL31_SOURCES += ${RK_GIC_SOURCES} \
drivers/arm/cci/cci.c \
drivers/console/aarch64/console.S \
drivers/ti/uart/aarch64/16550_console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/gpio/gpio.c \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a72.S \
plat/common/aarch64/platform_mp_stack.S \
${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
${RK_PLAT_COMMON}/bl31_plat_setup.c \
${RK_PLAT_COMMON}/params_setup.c \
${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \
${RK_PLAT_COMMON}/pmusram/pmu_sram.c \
${RK_PLAT_COMMON}/plat_pm.c \
${RK_PLAT_COMMON}/plat_topology.c \
${RK_PLAT_COMMON}/aarch64/platform_common.c \
${RK_PLAT_COMMON}/rockchip_sip_svc.c \
${RK_PLAT_SOC}/plat_sip_calls.c \
${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c \
${RK_PLAT_SOC}/drivers/pmu/m0_ctl.c \
${RK_PLAT_SOC}/drivers/pwm/pwm.c \
${RK_PLAT_SOC}/drivers/secure/secure.c \
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/drivers/dram/dfs.c \
${RK_PLAT_SOC}/drivers/dram/dram.c \
${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c \
${RK_PLAT_SOC}/drivers/dram/suspend.c
ENABLE_PLAT_COMPAT := 0
ENABLE_PLAT_COMPAT := 0
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))

121
plat/rockchip/rk3399/rk3399_def.h
View File

@ -31,122 +31,18 @@
#ifndef __PLAT_DEF_H__
#define __PLAT_DEF_H__
#define RK3399_PRIMARY_CPU 0x0
#include <addressmap.h>
#define RK3399_PRIMARY_CPU 0x0
/* Special value used to verify platform parameters from BL2 to BL3-1 */
#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
#define SIZE_K(n) ((n) * 1024)
#define SIZE_M(n) ((n) * 1024 * 1024)
/* Register base address and size */
#define MMIO_BASE 0xfe000000
#define GIC500_BASE (MMIO_BASE + 0xe00000)
#define GIC500_SIZE SIZE_M(2)
#define PMU_BASE (MMIO_BASE + 0x1310000)
#define PMU_SIZE SIZE_K(64)
#define PMUGRF_BASE (MMIO_BASE + 0x1320000)
#define PMUGRF_SIZE SIZE_K(64)
#define SGRF_BASE (MMIO_BASE + 0x1330000)
#define SGRF_SIZE SIZE_K(64)
#define PMUSRAM_BASE (MMIO_BASE + 0x13b0000)
#define PMUSRAM_SIZE SIZE_K(64)
#define PMUSRAM_RSIZE SIZE_K(8)
#define PWM_BASE (MMIO_BASE + 0x1420000)
#define PWM_SIZE SIZE_K(64)
#define CIC_BASE (MMIO_BASE + 0x1620000)
#define CIC_SIZE SIZE_K(4)
#define DCF_BASE (MMIO_BASE + 0x16a0000)
#define DCF_SIZE SIZE_K(4)
#define GPIO0_BASE (MMIO_BASE + 0x1720000)
#define GPIO0_SIZE SIZE_K(64)
#define GPIO1_BASE (MMIO_BASE + 0x1730000)
#define GPIO1_SIZE SIZE_K(64)
#define CRUS_BASE (MMIO_BASE + 0x1750000)
#define CRUS_SIZE SIZE_K(128)
#define GRF_BASE (MMIO_BASE + 0x1770000)
#define GRF_SIZE SIZE_K(64)
#define GPIO2_BASE (MMIO_BASE + 0x1780000)
#define GPIO2_SIZE SIZE_K(32)
#define GPIO3_BASE (MMIO_BASE + 0x1788000)
#define GPIO3_SIZE SIZE_K(32)
#define GPIO4_BASE (MMIO_BASE + 0x1790000)
#define GPIO4_SIZE SIZE_K(32)
#define STIME_BASE (MMIO_BASE + 0x1860000)
#define STIME_SIZE SIZE_K(64)
#define SRAM_BASE (MMIO_BASE + 0x18c0000)
#define SRAM_SIZE SIZE_K(192)
#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x1a50000)
#define NOC_0_SIZE SIZE_K(192)
#define DDRC0_BASE (MMIO_BASE + 0x1a80000)
#define DDRC0_SIZE SIZE_K(32)
#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x1a84000)
#define NOC_1_SIZE SIZE_K(16)
#define DDRC1_BASE (MMIO_BASE + 0x1a88000)
#define DDRC1_SIZE SIZE_K(32)
#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x1a8c000)
#define NOC_2_SIZE SIZE_K(16)
#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x1a90000)
#define NOC_3_SIZE SIZE_K(448)
#define CCI500_BASE (MMIO_BASE + 0x1b00000)
#define CCI500_SIZE SIZE_M(1)
#define DDR_PI_OFFSET 0x800
#define DDR_PHY_OFFSET 0x2000
#define DDRC0_PI_BASE (DDRC0_BASE + DDR_PI_OFFSET)
#define DDRC0_PHY_BASE (DDRC0_BASE + DDR_PHY_OFFSET)
#define DDRC1_PI_BASE (DDRC1_BASE + DDR_PI_OFFSET)
#define DDRC1_PHY_BASE (DDRC1_BASE + DDR_PHY_OFFSET)
/* Aggregate of all devices in the first GB */
#define RK3399_DEV_RNG0_BASE MMIO_BASE
#define RK3399_DEV_RNG0_SIZE 0x1d00000
/*
* include i2c pmu/audio, pwm0-3 rkpwm0-3 uart_dbg,mailbox scr
* 0xff650000 -0xff6c0000
*/
#define PD_BUS0_BASE (MMIO_BASE + 0x1650000)
#define PD_BUS0_SIZE SIZE_K(448)
#define PMUCRU_BASE (MMIO_BASE + 0x1750000)
#define CRU_BASE (MMIO_BASE + 0x1760000)
#define COLD_BOOT_BASE (MMIO_BASE + 0x1ff0000)
#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
/**************************************************************************
* UART related constants
**************************************************************************/
#define RK3399_UART2_BASE (0xff1a0000)
#define RK3399_UART2_SIZE SIZE_K(64)
#define RK3399_BAUDRATE (115200)
#define RK3399_UART_CLOCK (24000000)
#define RK3399_BAUDRATE 115200
#define RK3399_UART_CLOCK 24000000
/******************************************************************************
* System counter frequency related constants
@ -154,8 +50,8 @@
#define SYS_COUNTER_FREQ_IN_TICKS 24000000
/* Base rockchip_platform compatible GIC memory map */
#define BASE_GICD_BASE (GIC500_BASE)
#define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1))
#define BASE_GICD_BASE (GIC500_BASE)
#define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1))
/*****************************************************************************
* CCI-400 related constants
@ -176,6 +72,7 @@
#define ARM_IRQ_SEC_SGI_5 13
#define ARM_IRQ_SEC_SGI_6 14
#define ARM_IRQ_SEC_SGI_7 15
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated