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Tegra: add tzdram_base to plat_params_from_bl2 struct

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This patch adds another member, tzdram_base, to the plat_params_from_bl2 struct
in order to store the TZDRAM carveout base address used to load the Trusted OS.
The monitor programs the memory controller with the TZDRAM base and size in order
to deny any accesses from the NS world.

Change-Id: If39b8674d548175d7ccb6525c18d196ae8a8506c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2015-10-06 12:49:31 +05:30
parent 21f1fd95db
commit e0d4158c71
4 changed files with 24 additions and 7 deletions
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13
docs/plat/nvidia-tegra.md
View File

@ -62,6 +62,19 @@ TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> bl31'
Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=<value>' Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=<value>'
to the build command line. to the build command line.
The Tegra platform code expects a pointer to the following platform specific
structure via 'x1' register from the BL2 layer which is used by the
bl31_early_platform_setup() handler to extract the TZDRAM carveout base and
size for loading the Trusted OS. The Tegra memory controller driver programs
this base/size in order to restrict NS accesses.
typedef struct plat_params_from_bl2 {
/* TZ memory size */
uint64_t tzdram_size;
/* TZ memory base */
uint64_t tzdram_base;
} plat_params_from_bl2_t;
Power Management Power Management
================ ================
The PSCI implementation expects each platform to expose the 'power state' The PSCI implementation expects each platform to expose the 'power state'

13
plat/nvidia/tegra/common/tegra_bl31_setup.c
View File

@ -130,17 +130,18 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
* Copy BL3-3, BL3-2 entry point information. * Copy BL3-3, BL3-2 entry point information.
* They are stored in Secure RAM, in BL2's address space. * They are stored in Secure RAM, in BL2's address space.
*/ */
if (from_bl2->bl33_ep_info) assert(from_bl2->bl33_ep_info);
bl33_image_ep_info = *from_bl2->bl33_ep_info; bl33_image_ep_info = *from_bl2->bl33_ep_info;
if (from_bl2->bl32_ep_info) if (from_bl2->bl32_ep_info)
bl32_image_ep_info = *from_bl2->bl32_ep_info; bl32_image_ep_info = *from_bl2->bl32_ep_info;
/* /*
* Parse platform specific parameters - TZDRAM aperture size * Parse platform specific parameters - TZDRAM aperture base and size
*/ */
if (plat_params) assert(plat_params);
plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
} }
/******************************************************************************* /*******************************************************************************
@ -168,7 +169,7 @@ void bl31_platform_setup(void)
/* /*
* Do initial security configuration to allow DRAM/device access. * Do initial security configuration to allow DRAM/device access.
*/ */
tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, tegra_memctrl_tzdram_setup(plat_bl31_params_from_bl2.tzdram_base,
plat_bl31_params_from_bl2.tzdram_size); plat_bl31_params_from_bl2.tzdram_size);
/* Set the next EL to be AArch64 */ /* Set the next EL to be AArch64 */

2
plat/nvidia/tegra/common/tegra_pm.c
View File

@ -174,7 +174,7 @@ void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state)
* Security configuration to allow DRAM/device access. * Security configuration to allow DRAM/device access.
*/ */
plat_params = bl31_get_plat_params(); plat_params = bl31_get_plat_params();
tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
plat_params->tzdram_size); plat_params->tzdram_size);
} }

3
plat/nvidia/tegra/include/tegra_private.h
View File

@ -43,7 +43,10 @@
#define TEGRA_DRAM_END 0x27FFFFFFF #define TEGRA_DRAM_END 0x27FFFFFFF
typedef struct plat_params_from_bl2 { typedef struct plat_params_from_bl2 {
/* TZ memory size */
uint64_t tzdram_size; uint64_t tzdram_size;
/* TZ memory base */
uint64_t tzdram_base;
} plat_params_from_bl2_t; } plat_params_from_bl2_t;
/* Declarations for plat_psci_handlers.c */ /* Declarations for plat_psci_handlers.c */