CTCaer/switch-l4t-atf
1
0
Fork 0
mirror of https://github.com/CTCaer/switch-l4t-atf.git synced 2024-11-24 02:09:46 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Reduce space lost to object alignment

Browse Source 
Currently, sections within .text/.rodata/.data/.bss are emitted in the
order they are seen by the linker. This leads to wasted space, when a
section with a larger alignment follows one with a smaller alignment.
We can avoid this wasted space by sorting the sections.

To take full advantage of this, we must disable generation of common
symbols, so "common" data can be sorted along with the rest of .bss.

An example of the improvement, from `make DEBUG=1 PLAT=sun50i_a64 bl31`:
  .text   => no change
  .rodata => 16 bytes saved
  .data   => 11 bytes saved
  .bss    => 576 bytes saved

As a side effect, the addition of `-fno-common` in TF_CFLAGS makes it
easier to spot bugs in header files.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I073630a9b0b84e7302a7a500d4bb4b547be01d51
This commit is contained in:
Samuel Holland 2019-10-20 16:11:25 -05:00
parent 118a67a9a3
commit ebd6efae67
6 changed files with 34 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
Makefile
View File

@ -285,8 +285,9 @@ CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \
ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \
-ffreestanding -Wa,--fatal-warnings
TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \
-ffreestanding -fno-builtin -std=gnu99 \
-Os -ffunction-sections -fdata-sections
-ffunction-sections -fdata-sections \
-ffreestanding -fno-builtin -fno-common \
-Os -std=gnu99
ifeq (${SANITIZE_UB},on)
TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover

14
bl1/bl1.ld.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,7 +27,7 @@ SECTIONS
.text . : {
__TEXT_START__ = .;
*bl1_entrypoint.o(.text*)
*(.text*)
*(SORT_BY_ALIGNMENT(.text*))
*(.vectors)
. = ALIGN(PAGE_SIZE);
__TEXT_END__ = .;
@ -44,7 +44,7 @@ SECTIONS
.rodata . : {
__RODATA_START__ = .;
*(.rodata*)
*(SORT_BY_ALIGNMENT(.rodata*))
/* Ensure 8-byte alignment for descriptors and ensure inclusion */
. = ALIGN(8);
@ -72,8 +72,8 @@ SECTIONS
ro . : {
__RO_START__ = .;
*bl1_entrypoint.o(.text*)
*(.text*)
*(.rodata*)
*(SORT_BY_ALIGNMENT(.text*))
*(SORT_BY_ALIGNMENT(.rodata*))
/* Ensure 8-byte alignment for descriptors and ensure inclusion */
. = ALIGN(8);
@ -114,7 +114,7 @@ SECTIONS
*/
.data . : ALIGN(16) {
__DATA_RAM_START__ = .;
*(.data*)
*(SORT_BY_ALIGNMENT(.data*))
__DATA_RAM_END__ = .;
} >RAM AT>ROM
@ -131,7 +131,7 @@ SECTIONS
*/
.bss : ALIGN(16) {
__BSS_START__ = .;
*(.bss*)
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
__BSS_END__ = .;
} >RAM

12
bl2/bl2.ld.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,7 +27,7 @@ SECTIONS
.text . : {
__TEXT_START__ = .;
*bl2_entrypoint.o(.text*)
*(.text*)
*(SORT_BY_ALIGNMENT(.text*))
*(.vectors)
. = ALIGN(PAGE_SIZE);
__TEXT_END__ = .;
@ -44,7 +44,7 @@ SECTIONS
.rodata . : {
__RODATA_START__ = .;
*(.rodata*)
*(SORT_BY_ALIGNMENT(.rodata*))
/* Ensure 8-byte alignment for descriptors and ensure inclusion */
. = ALIGN(8);
@ -59,8 +59,8 @@ SECTIONS
ro . : {
__RO_START__ = .;
*bl2_entrypoint.o(.text*)
*(.text*)
*(.rodata*)
*(SORT_BY_ALIGNMENT(.text*))
*(SORT_BY_ALIGNMENT(.rodata*))
/* Ensure 8-byte alignment for descriptors and ensure inclusion */
. = ALIGN(8);
@ -93,7 +93,7 @@ SECTIONS
*/
.data . : {
__DATA_START__ = .;
*(.data*)
*(SORT_BY_ALIGNMENT(.data*))
__DATA_END__ = .;
} >RAM

12
bl2/bl2_el3.ld.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -44,7 +44,7 @@ SECTIONS
*bl2_el3_entrypoint.o(.text*)
*(.text.asm.*)
__TEXT_RESIDENT_END__ = .;
*(.text*)
*(SORT_BY_ALIGNMENT(.text*))
*(.vectors)
. = ALIGN(PAGE_SIZE);
__TEXT_END__ = .;
@ -52,7 +52,7 @@ SECTIONS
.rodata . : {
__RODATA_START__ = .;
*(.rodata*)
*(SORT_BY_ALIGNMENT(.rodata*))
/* Ensure 8-byte alignment for descriptors and ensure inclusion */
. = ALIGN(8);
@ -82,8 +82,8 @@ SECTIONS
*bl2_el3_entrypoint.o(.text*)
*(.text.asm.*)
__TEXT_RESIDENT_END__ = .;
*(.text*)
*(.rodata*)
*(SORT_BY_ALIGNMENT(.text*))
*(SORT_BY_ALIGNMENT(.rodata*))
/*
* Ensure 8-byte alignment for cpu_ops so that its fields are also
@ -135,7 +135,7 @@ SECTIONS
*/
.data . : {
__DATA_RAM_START__ = .;
*(.data*)
*(SORT_BY_ALIGNMENT(.data*))
__DATA_RAM_END__ = .;
} >RAM AT>ROM

12
bl2u/bl2u.ld.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,7 +27,7 @@ SECTIONS
.text . : {
__TEXT_START__ = .;
*bl2u_entrypoint.o(.text*)
*(.text*)
*(SORT_BY_ALIGNMENT(.text*))
*(.vectors)
. = ALIGN(PAGE_SIZE);
__TEXT_END__ = .;
@ -44,7 +44,7 @@ SECTIONS
.rodata . : {
__RODATA_START__ = .;
*(.rodata*)
*(SORT_BY_ALIGNMENT(.rodata*))
. = ALIGN(PAGE_SIZE);
__RODATA_END__ = .;
} >RAM
@ -52,8 +52,8 @@ SECTIONS
ro . : {
__RO_START__ = .;
*bl2u_entrypoint.o(.text*)
*(.text*)
*(.rodata*)
*(SORT_BY_ALIGNMENT(.text*))
*(SORT_BY_ALIGNMENT(.rodata*))
*(.vectors)
__RO_END_UNALIGNED__ = .;
@ -80,7 +80,7 @@ SECTIONS
*/
.data . : {
__DATA_START__ = .;
*(.data*)
*(SORT_BY_ALIGNMENT(.data*))
__DATA_END__ = .;
} >RAM

12
bl31/bl31.ld.S
View File

@ -33,7 +33,7 @@ SECTIONS
.text . : {
__TEXT_START__ = .;
*bl31_entrypoint.o(.text*)
*(.text*)
*(SORT_BY_ALIGNMENT(.text*))
*(.vectors)
. = ALIGN(PAGE_SIZE);
__TEXT_END__ = .;
@ -41,7 +41,7 @@ SECTIONS
.rodata . : {
__RODATA_START__ = .;
*(.rodata*)
*(SORT_BY_ALIGNMENT(.rodata*))
/* Ensure 8-byte alignment for descriptors and ensure inclusion */
. = ALIGN(8);
@ -87,8 +87,8 @@ SECTIONS
ro . : {
__RO_START__ = .;
*bl31_entrypoint.o(.text*)
*(.text*)
*(.rodata*)
*(SORT_BY_ALIGNMENT(.text*))
*(SORT_BY_ALIGNMENT(.rodata*))
/* Ensure 8-byte alignment for descriptors and ensure inclusion */
. = ALIGN(8);
@ -179,7 +179,7 @@ SECTIONS
*/
.data . : {
__DATA_START__ = .;
*(.data*)
*(SORT_BY_ALIGNMENT(.data*))
__DATA_END__ = .;
} >RAM
@ -211,7 +211,7 @@ SECTIONS
*/
.bss (NOLOAD) : ALIGN(16) {
__BSS_START__ = .;
*(.bss*)
*(SORT_BY_ALIGNMENT(.bss*))
*(COMMON)
#if !USE_COHERENT_MEM
/*