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Tegra: common: improve cyclomatic complexity
Code complexity is a good indication of maintainability versus testability of a piece of software. ISO26262 introduces the following thresholds: complexity < 10 is accepted 10 <= complexity < 20 has to be justified complexity >= 20 cannot be accepted Rationale is that number of test cases to fully test a piece of software can (depending on the coverage metrics) grow exponentially with the number of branches in the software. This patch removes redundant conditionals from 'bl31_early_platform_setup' handler to reduce the McCabe Cyclomatic Complexity for this function. Change-Id: Ifb628e33269b388f9323639cd97db761a7e049c4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -1,5 +1,6 @@
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/*
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/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -102,7 +103,6 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
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struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
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plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
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plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
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image_info_t bl32_img_info = { {0} };
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image_info_t bl32_img_info = { {0} };
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uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
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int32_t ret;
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int32_t ret;
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/*
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/*
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@ -163,20 +163,17 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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* location to store the boot profiler logs. Sanity check the
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* location to store the boot profiler logs. Sanity check the
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* address and initialise the profiler library, if it looks ok.
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* address and initialise the profiler library, if it looks ok.
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*/
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*/
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if (plat_params->boot_profiler_shmem_base != 0ULL) {
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ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
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PROFILER_SIZE_BYTES);
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if (ret == (int32_t)0) {
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ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
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/* store the membase for the profiler lib */
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PROFILER_SIZE_BYTES);
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plat_bl31_params_from_bl2.boot_profiler_shmem_base =
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if (ret == (int32_t)0) {
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plat_params->boot_profiler_shmem_base;
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/* store the membase for the profiler lib */
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/* initialise the profiler library */
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plat_bl31_params_from_bl2.boot_profiler_shmem_base =
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boot_profiler_init(plat_params->boot_profiler_shmem_base,
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plat_params->boot_profiler_shmem_base;
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TEGRA_TMRUS_BASE);
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/* initialise the profiler library */
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boot_profiler_init(plat_params->boot_profiler_shmem_base,
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TEGRA_TMRUS_BASE);
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}
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}
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}
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/*
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/*
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@ -205,6 +202,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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*/
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*/
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if (arg_from_bl2->bl32_image_info != NULL) {
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if (arg_from_bl2->bl32_image_info != NULL) {
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uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
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bl32_img_info = *arg_from_bl2->bl32_image_info;
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bl32_img_info = *arg_from_bl2->bl32_image_info;
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/* Relocate BL32 if it resides outside of the TZDRAM */
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/* Relocate BL32 if it resides outside of the TZDRAM */
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