mirror of
https://github.com/CTCaer/switch-l4t-atf.git
synced 2025-02-25 21:22:18 +00:00
Merge changes from topic "erratas" into integration
* changes: errata: workaround for Neoverse N2 erratum 2138956 errata: workaround for Neoverse N2 erratum 2189731 errata: workaround for Cortex-A710 erratum 2017096 errata: workaround for Cortex-A710 erratum 2055002
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
ef03e78f42
@ -381,6 +381,14 @@ For Cortex-A710, the following errata build flags are defined :
|
||||
Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
|
||||
r2p0 of the CPU. It is still open.
|
||||
|
||||
- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
|
||||
and is still open.
|
||||
|
||||
- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to
|
||||
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
|
||||
of the CPU and is still open.
|
||||
|
||||
For Neoverse N2, the following errata build flags are defined :
|
||||
|
||||
- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
|
||||
@ -389,6 +397,12 @@ For Neoverse N2, the following errata build flags are defined :
|
||||
- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
|
||||
CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
|
||||
|
||||
DSU Errata Workarounds
|
||||
----------------------
|
||||
|
||||
|
||||
@ -13,6 +13,7 @@
|
||||
* CPU Extended Control register specific definitions
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4
|
||||
#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Power Control register specific definitions
|
||||
@ -20,4 +21,10 @@
|
||||
#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
||||
#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register specific definitions.
|
||||
******************************************************************************/
|
||||
#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
|
||||
#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
|
||||
|
||||
#endif /* CORTEX_A710_H */
|
||||
|
||||
@ -35,4 +35,10 @@
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
|
||||
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
||||
|
||||
/*******************************************************************************
|
||||
* CPU Auxiliary Control register 5 specific definitions.
|
||||
******************************************************************************/
|
||||
#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
|
||||
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
|
||||
|
||||
#endif /* NEOVERSE_N2_H */
|
||||
|
||||
@ -107,6 +107,59 @@ func check_errata_2081180
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2081180
|
||||
|
||||
/* ---------------------------------------------------------------------
|
||||
* Errata Workaround for Cortex-A710 Erratum 2055002.
|
||||
* This applies to revision r1p0, r2p0 of Cortex-A710 and is still open.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0-x17
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
func errata_a710_2055002_wa
|
||||
/* Compare x0 against revision r2p0 */
|
||||
mov x17, x30
|
||||
bl check_errata_2055002
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_A710_CPUACTLR_EL1
|
||||
orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46
|
||||
msr CORTEX_A710_CPUACTLR_EL1, x1
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a710_2055002_wa
|
||||
|
||||
func check_errata_2055002
|
||||
/* Applies to r1p0, r2p0 */
|
||||
mov x1, #0x20
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2055002
|
||||
|
||||
/* -------------------------------------------------------------
|
||||
* Errata Workaround for Cortex-A710 Erratum 2017096.
|
||||
* This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0-x17
|
||||
* -------------------------------------------------------------
|
||||
*/
|
||||
func errata_a710_2017096_wa
|
||||
/* Compare x0 against revision r0p0 to r2p0 */
|
||||
mov x17, x30
|
||||
bl check_errata_2017096
|
||||
cbz x0, 1f
|
||||
mrs x1, CORTEX_A710_CPUECTLR_EL1
|
||||
orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
|
||||
msr CORTEX_A710_CPUECTLR_EL1, x1
|
||||
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_a710_2017096_wa
|
||||
|
||||
func check_errata_2017096
|
||||
/* Applies to r0p0, r1p0, r2p0 */
|
||||
mov x1, #0x20
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2017096
|
||||
|
||||
/* ----------------------------------------------------
|
||||
* HW will do the cache maintenance while powering down
|
||||
* ----------------------------------------------------
|
||||
@ -123,10 +176,10 @@ func cortex_a710_core_pwr_dwn
|
||||
ret
|
||||
endfunc cortex_a710_core_pwr_dwn
|
||||
|
||||
/*
|
||||
* Errata printing function for Cortex A710. Must follow AAPCS.
|
||||
*/
|
||||
#if REPORT_ERRATA
|
||||
/*
|
||||
* Errata printing function for Cortex-A710. Must follow AAPCS.
|
||||
*/
|
||||
func cortex_a710_errata_report
|
||||
stp x8, x30, [sp, #-16]!
|
||||
|
||||
@ -139,6 +192,8 @@ func cortex_a710_errata_report
|
||||
*/
|
||||
report_errata ERRATA_A710_1987031, cortex_a710, 1987031
|
||||
report_errata ERRATA_A710_2081180, cortex_a710, 2081180
|
||||
report_errata ERRATA_A710_2055002, cortex_a710, 2055002
|
||||
report_errata ERRATA_A710_2017096, cortex_a710, 2017096
|
||||
|
||||
ldp x8, x30, [sp], #16
|
||||
ret
|
||||
@ -164,8 +219,17 @@ func cortex_a710_reset_func
|
||||
bl errata_a710_2081180_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A710_2055002
|
||||
mov x0, x18
|
||||
bl errata_a710_2055002_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_A710_2017096
|
||||
mov x0, x18
|
||||
bl errata_a710_2017096_wa
|
||||
#endif
|
||||
isb
|
||||
ret x19
|
||||
ret x19
|
||||
endfunc cortex_a710_reset_func
|
||||
|
||||
/* ---------------------------------------------
|
||||
|
||||
@ -114,6 +114,75 @@ func check_errata_2025414
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2025414
|
||||
|
||||
/* ---------------------------------------------------------------
|
||||
* Errata Workaround for Neoverse N2 Erratum 2189731.
|
||||
* This applies to revision r0p0 of Neoverse N2 and is still open.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0-x17
|
||||
* ---------------------------------------------------------------
|
||||
*/
|
||||
func errata_n2_2189731_wa
|
||||
/* Compare x0 against revision r0p0 */
|
||||
mov x17, x30
|
||||
bl check_errata_2189731
|
||||
cbz x0, 1f
|
||||
mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
|
||||
orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
|
||||
msr NEOVERSE_N2_CPUACTLR5_EL1, x1
|
||||
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_n2_2189731_wa
|
||||
|
||||
func check_errata_2189731
|
||||
/* Applies to r0p0 */
|
||||
mov x1, #0x00
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2189731
|
||||
|
||||
/* --------------------------------------------------
|
||||
* Errata Workaround for Neoverse N2 Erratum 2138956.
|
||||
* This applies to revision r0p0 of Neoverse N2. it is still open.
|
||||
* Inputs:
|
||||
* x0: variant[4:7] and revision[0:3] of current cpu.
|
||||
* Shall clobber: x0-x17
|
||||
* --------------------------------------------------
|
||||
*/
|
||||
func errata_n2_2138956_wa
|
||||
/* Check revision. */
|
||||
mov x17, x30
|
||||
bl check_errata_2138956
|
||||
cbz x0, 1f
|
||||
|
||||
/* Apply instruction patching sequence */
|
||||
ldr x0,=0x3
|
||||
msr S3_6_c15_c8_0,x0
|
||||
ldr x0,=0xF3A08002
|
||||
msr S3_6_c15_c8_2,x0
|
||||
ldr x0,=0xFFF0F7FE
|
||||
msr S3_6_c15_c8_3,x0
|
||||
ldr x0,=0x10002001003FF
|
||||
msr S3_6_c15_c8_1,x0
|
||||
ldr x0,=0x4
|
||||
msr S3_6_c15_c8_0,x0
|
||||
ldr x0,=0xBF200000
|
||||
msr S3_6_c15_c8_2,x0
|
||||
ldr x0,=0xFFEF0000
|
||||
msr S3_6_c15_c8_3,x0
|
||||
ldr x0,=0x10002001003F3
|
||||
msr S3_6_c15_c8_1,x0
|
||||
isb
|
||||
1:
|
||||
ret x17
|
||||
endfunc errata_n2_2138956_wa
|
||||
|
||||
func check_errata_2138956
|
||||
/* Applies to r0p0 */
|
||||
mov x1, #0x00
|
||||
b cpu_rev_var_ls
|
||||
endfunc check_errata_2138956
|
||||
|
||||
/* -------------------------------------------
|
||||
* The CPU Ops reset function for Neoverse N2.
|
||||
* -------------------------------------------
|
||||
@ -144,6 +213,17 @@ func neoverse_n2_reset_func
|
||||
bl errata_n2_2025414_wa
|
||||
#endif
|
||||
|
||||
#if ERRATA_N2_2189731
|
||||
mov x0, x18
|
||||
bl errata_n2_2189731_wa
|
||||
#endif
|
||||
|
||||
|
||||
#if ERRATA_N2_2138956
|
||||
mov x0, x18
|
||||
bl errata_n2_2138956_wa
|
||||
#endif
|
||||
|
||||
#if ENABLE_AMU
|
||||
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
|
||||
mrs x0, cptr_el3
|
||||
@ -207,6 +287,8 @@ func neoverse_n2_errata_report
|
||||
report_errata ERRATA_N2_2002655, neoverse_n2, 2002655
|
||||
report_errata ERRATA_N2_2067956, neoverse_n2, 2067956
|
||||
report_errata ERRATA_N2_2025414, neoverse_n2, 2025414
|
||||
report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
|
||||
report_errata ERRATA_N2_2138956, neoverse_n2, 2138956
|
||||
|
||||
ldp x8, x30, [sp], #16
|
||||
ret
|
||||
|
||||
@ -433,6 +433,22 @@ ERRATA_N2_2067956 ?=0
|
||||
# to revision r0p0 of the Neoverse N2 cpu and is still open.
|
||||
ERRATA_N2_2025414 ?=0
|
||||
|
||||
# Flag to apply erratum 2189731 workaround during reset. This erratum applies
|
||||
# to revision r0p0 of the Neoverse N2 cpu and is still open.
|
||||
ERRATA_N2_2189731 ?=0
|
||||
|
||||
# Flag to apply erratum 2138956 workaround during reset. This erratum applies
|
||||
# to revision r0p0 of the Neoverse N2 cpu and is still open.
|
||||
ERRATA_N2_2138956 ?=0
|
||||
|
||||
# Flag to apply erratum 2055002 workaround during reset. This erratum applies
|
||||
# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
|
||||
ERRATA_A710_2055002 ?=0
|
||||
|
||||
# Flag to apply erratum 2017096 workaround during reset. This erratum applies
|
||||
# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
|
||||
ERRATA_A710_2017096 ?=0
|
||||
|
||||
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
|
||||
# Applying the workaround results in higher DSU power consumption on idle.
|
||||
ERRATA_DSU_798953 ?=0
|
||||
@ -798,6 +814,22 @@ $(eval $(call add_define,ERRATA_N2_2067956))
|
||||
$(eval $(call assert_boolean,ERRATA_N2_2025414))
|
||||
$(eval $(call add_define,ERRATA_N2_2025414))
|
||||
|
||||
# Process ERRATA_N2_2189731 flag
|
||||
$(eval $(call assert_boolean,ERRATA_N2_2189731))
|
||||
$(eval $(call add_define,ERRATA_N2_2189731))
|
||||
|
||||
# Process ERRATA_N2_2138956 flag
|
||||
$(eval $(call assert_boolean,ERRATA_N2_2138956))
|
||||
$(eval $(call add_define,ERRATA_N2_2138956))
|
||||
|
||||
# Process ERRATA_A710_2055002 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A710_2055002))
|
||||
$(eval $(call add_define,ERRATA_A710_2055002))
|
||||
|
||||
# Process ERRATA_A710_2017096 flag
|
||||
$(eval $(call assert_boolean,ERRATA_A710_2017096))
|
||||
$(eval $(call add_define,ERRATA_A710_2017096))
|
||||
|
||||
# Process ERRATA_DSU_798953 flag
|
||||
$(eval $(call assert_boolean,ERRATA_DSU_798953))
|
||||
$(eval $(call add_define,ERRATA_DSU_798953))
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user