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Merge pull request #184 from jcastillo-arm/jc/tf-issues/100
FVP: make usage of Trusted DRAM optional at build time
This commit is contained in:
commit
f0e240d7f5
@ -35,8 +35,8 @@ OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl1_entrypoint)
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MEMORY {
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ROM (rx): ORIGIN = TZROM_BASE, LENGTH = TZROM_SIZE
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RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
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ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT
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RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT
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}
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SECTIONS
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@ -35,7 +35,7 @@ OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl2_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
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RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT
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}
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@ -36,7 +36,7 @@ ENTRY(bl31_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
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RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT
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}
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@ -955,22 +955,95 @@ PROGBITS sections then the resulting binary file would contain a bunch of zero
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bytes at the location of this NOBITS section, making the image unnecessarily
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bigger. Smaller images allow faster loading from the FIP to the main memory.
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On FVP platforms, we use the Trusted ROM and Trusted SRAM to store the trusted
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firmware binaries.
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On FVP platforms, we use the Trusted ROM, Trusted SRAM and, optionally, Trusted
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DRAM to store the trusted firmware binaries and shared data.
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* A 4KB page of shared memory is used to store the entrypoint mailboxes
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and the parameters passed between bootloaders. The shared memory can be
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allocated either at the top of Trusted SRAM or at the base of Trusted
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DRAM at build time. When allocated in Trusted SRAM, the amount of Trusted
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SRAM available to load the bootloader images will be reduced by the size
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of the shared memory.
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* BL1 is originally sitting in the Trusted ROM at address `0x0`. Its
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read-write data are relocated at the top of the Trusted SRAM at runtime.
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If the shared memory is allocated in Trusted SRAM, the BL1 read-write data
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is relocated just below the shared memory.
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* BL3-1 is loaded at the top of the Trusted SRAM, such that its NOBITS
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sections will overwrite BL1 R/W data.
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* BL2 is loaded below BL3-1.
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* The TSP is loaded as the BL3-2 image at the base of the Trusted SRAM. Its
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NOBITS sections are allowed to overlay BL2.
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* The TSP is loaded as the BL3-2 image at the base of either the Trusted
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SRAM or Trusted DRAM. When loaded into Trusted SRAM, its NOBITS sections
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are allowed to overlay BL2. When loaded into Trusted DRAM, an offset
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corresponding to the size of the shared memory is applied to avoid
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overlap.
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This memory layout is designed to give the BL3-2 image as much memory as
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possible. It is illustrated by the following diagram.
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possible when it is loaded into Trusted SRAM. Depending on the location of the
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shared memory page and the TSP, it will result in different memory maps,
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illustrated by the following diagrams.
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** Shared data & TSP in Trusted SRAM (default option): **
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Trusted SRAM
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0x04040000 +----------+
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| Shared |
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0x0403F000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL3-1 PROGBITS |
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|----------| ------------------
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| BL2 | <<<<<<<<<<<<< | BL3-2 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL3-2 PROGBITS |
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0x04000000 +----------+ ------------------
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Trusted ROM
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0x04000000 +----------+
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| BL1 (ro) |
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0x00000000 +----------+
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** Shared data & TSP in Trusted DRAM: **
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Trusted DRAM
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0x08000000 +----------+
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| |
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| BL3-2 |
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| |
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0x06001000 |----------|
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| Shared |
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0x06000000 +----------+
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Trusted SRAM
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0x04040000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL3-1 PROGBITS |
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|----------| ------------------
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| BL2 |
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|----------|
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| |
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0x04000000 +----------+
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Trusted ROM
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0x04000000 +----------+
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| BL1 (ro) |
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0x00000000 +----------+
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** Shared data in Trusted DRAM, TSP in Trusted SRAM: **
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Trusted DRAM
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0x08000000 +----------+
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| |
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| |
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| |
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0x06001000 |----------|
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| Shared |
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0x06000000 +----------+
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Trusted SRAM
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0x04040000 +----------+ loaded by BL2 ------------------
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@ -988,8 +1061,8 @@ possible. It is illustrated by the following diagram.
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| BL1 (ro) |
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0x00000000 +----------+
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The TSP image may be loaded in Trusted DRAM instead. This doesn't change the
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memory layout of the other boot loader images in Trusted SRAM.
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Loading the TSP image in Trusted DRAM doesn't change the memory layout of the
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other boot loader images in Trusted SRAM.
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Each bootloader stage image layout is described by its own linker script. The
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linker scripts export some symbols into the program symbol table. Their values
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@ -150,31 +150,6 @@ file is found in [plat/fvp/include/platform_def.h].
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Defines the total number of nodes in the affinity heirarchy at all affinity
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levels used by the platform.
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* **#define : TZROM_BASE**
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Defines the base address of secure ROM on the platform, where the BL1 binary
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is loaded. This constant is used by the linker scripts to ensure that the
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BL1 image fits into the available memory.
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* **#define : TZROM_SIZE**
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Defines the size of secure ROM on the platform. This constant is used by the
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linker scripts to ensure that the BL1 image fits into the available memory.
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* **#define : TZRAM_BASE**
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Defines the base address of the secure RAM on platform, where the data
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section of the BL1 binary is loaded. The BL2 and BL3-1 images are also
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loaded in this secure RAM region. This constant is used by the linker
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scripts to ensure that the BL1 data section and BL2/BL3-1 binary images fit
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into the available memory.
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* **#define : TZRAM_SIZE**
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Defines the size of the secure RAM on the platform. This constant is used by
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the linker scripts to ensure that the BL1 data section and BL2/BL3-1 binary
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images fit into the available memory.
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* **#define : BL1_RO_BASE**
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Defines the base address in secure ROM where BL1 originally lives. Must be
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@ -133,6 +133,8 @@ the build system doesn't track dependency for build options. Therefore, if any
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of the build options are changed from a previous build, a clean build must be
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performed.
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#### Common build options
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* `BL30`: Path to BL3-0 image in the host file system. This image is optional.
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If a BL3-0 image is present then this option must be passed for the `fip`
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target
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@ -205,6 +207,19 @@ performed.
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synchronous method) or 1 (BL3-2 is initialized using asynchronous method).
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Default is 0.
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#### FVP specific build options
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* `FVP_SHARED_DATA_LOCATION`: location of the shared memory page. Available
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options:
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- 'tsram' (default) : top of Trusted SRAM
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- 'tdram' : base of Trusted DRAM
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* `FVP_TSP_RAM_LOCATION`: location of the TSP binary. Options:
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- 'tsram' (default) : base of Trusted SRAM
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- 'tdram' : Trusted DRAM (above shared data)
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For a better understanding of FVP options, the FVP memory map is detailed in
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[Firmware Design].
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### Creating a Firmware Image Package
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@ -327,11 +342,11 @@ The Firmware Package contains this new image:
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On FVP, the TSP binary runs from Trusted SRAM by default. It is also possible
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to run it from Trusted DRAM. This is controlled by the build configuration
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`TSP_RAM_LOCATION`:
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`FVP_TSP_RAM_LOCATION`:
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CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- \
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BL33=<path-to>/<bl33_image> \
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make PLAT=fvp SPD=tspd TSP_RAM_LOCATION=tdram all fip
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make PLAT=fvp SPD=tspd FVP_TSP_RAM_LOCATION=tdram all fip
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### Checking source code style
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@ -56,9 +56,9 @@ plat_config_t plat_config;
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* configure_mmu_elx() will give the available subset of that,
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*/
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const mmap_region_t fvp_mmap[] = {
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{ TZROM_BASE, TZROM_BASE, TZROM_SIZE,
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MT_MEMORY | MT_RO | MT_SECURE },
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{ TZDRAM_BASE, TZDRAM_BASE, TZDRAM_SIZE,
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{ FVP_SHARED_RAM_BASE, FVP_SHARED_RAM_BASE, FVP_SHARED_RAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE },
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{ FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_BASE, FVP_TRUSTED_DRAM_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE },
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{ FLASH0_BASE, FLASH0_BASE, FLASH0_SIZE,
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MT_MEMORY | MT_RO | MT_SECURE },
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@ -34,7 +34,7 @@
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#include <gic_v2.h>
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#include <pl011.h>
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#include "../drivers/pwrc/fvp_pwrc.h"
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#include "../fvp_def.h"
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#include "platform_def.h"
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.globl platform_get_entrypoint
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.globl plat_secondary_cold_boot_setup
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@ -140,7 +140,7 @@ warm_reset:
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* its safe to read it here with SO attributes
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* ---------------------------------------------
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*/
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ldr x10, =TZDRAM_BASE + MBOX_OFF
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ldr x10, =MBOX_BASE
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bl platform_get_core_pos
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lsl x0, x0, #CACHE_WRITEBACK_SHIFT
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ldr x0, [x10, x0]
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@ -153,8 +153,8 @@ _panic: b _panic
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/* -----------------------------------------------------
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* void platform_mem_init (void);
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*
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* Zero out the mailbox registers in the TZDRAM. The
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* mmu is turned off right now and only the primary can
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* Zero out the mailbox registers in the shared memory.
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* The mmu is turned off right now and only the primary can
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* ever execute this code. Secondaries will read the
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* mailboxes using SO accesses. In short, BL31 will
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* update the mailboxes after mapping the tzdram as
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@ -163,7 +163,7 @@ _panic: b _panic
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* -----------------------------------------------------
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*/
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func platform_mem_init
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ldr x0, =TZDRAM_BASE + MBOX_OFF
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ldr x0, =MBOX_BASE
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mov w1, #PLATFORM_CORE_COUNT
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loop:
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str xzr, [x0], #CACHE_WRITEBACK_GRANULE
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@ -76,12 +76,12 @@ void bl1_early_platform_setup(void)
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console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = TZRAM_BASE;
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bl1_tzram_layout.total_size = TZRAM_SIZE;
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bl1_tzram_layout.total_base = FVP_TRUSTED_SRAM_BASE;
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bl1_tzram_layout.total_size = FVP_TRUSTED_SRAM_SIZE;
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/* Calculate how much RAM BL1 is using and how much remains free */
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bl1_tzram_layout.free_base = TZRAM_BASE;
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bl1_tzram_layout.free_size = TZRAM_SIZE;
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bl1_tzram_layout.free_base = FVP_TRUSTED_SRAM_BASE;
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bl1_tzram_layout.free_size = FVP_TRUSTED_SRAM_SIZE;
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reserve_mem(&bl1_tzram_layout.free_base,
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&bl1_tzram_layout.free_size,
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BL1_RAM_BASE,
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@ -114,8 +114,8 @@ void bl1_plat_arch_setup(void)
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fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
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bl1_tzram_layout.total_size,
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TZROM_BASE,
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TZROM_BASE + TZROM_SIZE,
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BL1_RO_BASE,
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BL1_RO_LIMIT,
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BL1_COHERENT_RAM_BASE,
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BL1_COHERENT_RAM_LIMIT);
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}
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@ -72,6 +72,11 @@ static meminfo_t bl2_tzram_layout
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__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
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section("tzfw_coherent_mem")));
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/* Assert that BL3-1 parameters fit in shared memory */
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CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) <
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(FVP_SHARED_RAM_BASE + FVP_SHARED_RAM_SIZE),
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assert_bl31_params_do_not_fit_in_shared_memory);
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/*******************************************************************************
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* Reference to structures which holds the arguments which need to be passed
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* to BL31
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@ -97,14 +102,6 @@ bl31_params_t *bl2_plat_get_bl31_params(void)
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{
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bl2_to_bl31_params_mem_t *bl31_params_mem;
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#if TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
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/*
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* Ensure that the secure DRAM memory used for passing BL31 arguments
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* does not overlap with the BL32_BASE.
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*/
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assert(BL32_BASE > PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t));
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#endif
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/*
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* Allocate the memory for all the arguments that needs to
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* be passed to BL31
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@ -1,4 +1,4 @@
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#/*
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/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -31,19 +31,29 @@
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#ifndef __FVP_DEF_H__
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#define __FVP_DEF_H__
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#include <platform_def.h> /* for TZROM_SIZE */
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/* Firmware Image Package */
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#define FIP_IMAGE_NAME "fip.bin"
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#define FVP_PRIMARY_CPU 0x0
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/* Memory location options for Shared data and TSP in FVP */
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#define FVP_IN_TRUSTED_SRAM 0
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#define FVP_IN_TRUSTED_DRAM 1
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/*******************************************************************************
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* FVP memory map related constants
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******************************************************************************/
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#define FVP_TRUSTED_ROM_BASE 0x00000000
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#define FVP_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */
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#define FVP_TRUSTED_SRAM_BASE 0x04000000
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#define FVP_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */
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#define FVP_TRUSTED_DRAM_BASE 0x06000000
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#define FVP_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */
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#define FLASH0_BASE 0x08000000
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#define FLASH0_SIZE TZROM_SIZE
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#define FLASH0_SIZE 0x04000000
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#define FLASH1_BASE 0x0c000000
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#define FLASH1_SIZE 0x04000000
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@ -64,10 +74,27 @@
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x10000
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#define MBOX_OFF 0x1000
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/* 4KB shared memory */
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#define FVP_SHARED_RAM_SIZE 0x1000
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/* Base address where parameters to BL31 are stored */
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#define PARAMS_BASE TZDRAM_BASE
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/* Location of shared memory */
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#if (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_DRAM)
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/* Shared memory at the base of Trusted DRAM */
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# define FVP_SHARED_RAM_BASE FVP_TRUSTED_DRAM_BASE
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# define FVP_TRUSTED_SRAM_LIMIT (FVP_TRUSTED_SRAM_BASE \
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+ FVP_TRUSTED_SRAM_SIZE)
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#elif (FVP_SHARED_DATA_LOCATION_ID == FVP_IN_TRUSTED_SRAM)
|
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# if (FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM)
|
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# error "Shared data in Trusted SRAM and TSP in Trusted DRAM is not supported"
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# endif
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/* Shared memory at the top of the Trusted SRAM */
|
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# define FVP_SHARED_RAM_BASE (FVP_TRUSTED_SRAM_BASE \
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+ FVP_TRUSTED_SRAM_SIZE \
|
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- FVP_SHARED_RAM_SIZE)
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# define FVP_TRUSTED_SRAM_LIMIT FVP_SHARED_RAM_BASE
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#else
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# error "Unsupported FVP_SHARED_DATA_LOCATION_ID value"
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#endif
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#define DRAM1_BASE 0x80000000ull
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#define DRAM1_SIZE 0x80000000ull
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@ -229,5 +256,15 @@
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#define FVP_NSAID_HDLCD0 2
|
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#define FVP_NSAID_CLCD 7
|
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/*******************************************************************************
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* Shared Data
|
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******************************************************************************/
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/* Entrypoint mailboxes */
|
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#define MBOX_BASE FVP_SHARED_RAM_BASE
|
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#define MBOX_SIZE 0x200
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/* Base address where parameters to BL31 are stored */
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#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE)
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#endif /* __FVP_DEF_H__ */
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|
@ -103,7 +103,7 @@ int fvp_affinst_on(unsigned long mpidr,
|
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} while (psysr & PSYSR_AFF_L0);
|
||||
|
||||
linear_id = platform_get_core_pos(mpidr);
|
||||
fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
|
||||
fvp_mboxes = (mailbox_t *)MBOX_BASE;
|
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fvp_mboxes[linear_id].value = sec_entrypoint;
|
||||
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
|
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sizeof(unsigned long));
|
||||
@ -240,7 +240,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
|
||||
|
||||
/* Program the jump address for the target cpu */
|
||||
linear_id = platform_get_core_pos(mpidr);
|
||||
fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
|
||||
fvp_mboxes = (mailbox_t *)MBOX_BASE;
|
||||
fvp_mboxes[linear_id].value = sec_entrypoint;
|
||||
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
|
||||
sizeof(unsigned long));
|
||||
@ -329,7 +329,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
|
||||
fvp_pwrc_clr_wen(mpidr);
|
||||
|
||||
/* Zero the jump address in the mailbox for this cpu */
|
||||
fvp_mboxes = (mailbox_t *) (TZDRAM_BASE + MBOX_OFF);
|
||||
fvp_mboxes = (mailbox_t *)MBOX_BASE;
|
||||
linear_id = platform_get_core_pos(mpidr);
|
||||
fvp_mboxes[linear_id].value = 0;
|
||||
flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
|
||||
|
@ -32,6 +32,7 @@
|
||||
#define __PLATFORM_DEF_H__
|
||||
|
||||
#include <arch.h>
|
||||
#include <../fvp_def.h>
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
@ -83,32 +84,21 @@
|
||||
#define MAX_IO_DEVICES 3
|
||||
#define MAX_IO_HANDLES 4
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform memory map related constants
|
||||
******************************************************************************/
|
||||
#define TZROM_BASE 0x00000000
|
||||
#define TZROM_SIZE 0x04000000
|
||||
|
||||
#define TZRAM_BASE 0x04000000
|
||||
#define TZRAM_SIZE 0x40000
|
||||
|
||||
/* Location of trusted dram on the base fvp */
|
||||
#define TZDRAM_BASE 0x06000000
|
||||
#define TZDRAM_SIZE 0x02000000
|
||||
|
||||
/*******************************************************************************
|
||||
* BL1 specific defines.
|
||||
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
|
||||
* addresses.
|
||||
******************************************************************************/
|
||||
#define BL1_RO_BASE TZROM_BASE
|
||||
#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
|
||||
#define BL1_RO_BASE FVP_TRUSTED_ROM_BASE
|
||||
#define BL1_RO_LIMIT (FVP_TRUSTED_ROM_BASE \
|
||||
+ FVP_TRUSTED_ROM_SIZE)
|
||||
/*
|
||||
* Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
|
||||
* the current BL1 RW debug size plus a little space for growth.
|
||||
* Put BL1 RW at the top of the Trusted SRAM (just below the shared memory, if
|
||||
* present). BL1_RW_BASE is calculated using the current BL1 RW debug size plus
|
||||
* a little space for growth.
|
||||
*/
|
||||
#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x6000)
|
||||
#define BL1_RW_LIMIT (TZRAM_BASE + TZRAM_SIZE)
|
||||
#define BL1_RW_BASE (FVP_TRUSTED_SRAM_LIMIT - 0x6000)
|
||||
#define BL1_RW_LIMIT FVP_TRUSTED_SRAM_LIMIT
|
||||
|
||||
/*******************************************************************************
|
||||
* BL2 specific defines.
|
||||
@ -124,12 +114,13 @@
|
||||
* BL31 specific defines.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
|
||||
* current BL3-1 debug size plus a little space for growth.
|
||||
* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
|
||||
* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
|
||||
* little space for growth.
|
||||
*/
|
||||
#define BL31_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1D000)
|
||||
#define BL31_BASE (FVP_TRUSTED_SRAM_LIMIT - 0x1D000)
|
||||
#define BL31_PROGBITS_LIMIT BL1_RW_BASE
|
||||
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
|
||||
#define BL31_LIMIT FVP_TRUSTED_SRAM_LIMIT
|
||||
|
||||
/*******************************************************************************
|
||||
* BL32 specific defines.
|
||||
@ -137,22 +128,20 @@
|
||||
/*
|
||||
* On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
|
||||
*/
|
||||
#define TSP_IN_TZRAM 0
|
||||
#define TSP_IN_TZDRAM 1
|
||||
|
||||
#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
|
||||
# define TSP_SEC_MEM_BASE TZRAM_BASE
|
||||
# define TSP_SEC_MEM_SIZE TZRAM_SIZE
|
||||
# define BL32_BASE TZRAM_BASE
|
||||
#if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_SRAM
|
||||
# define TSP_SEC_MEM_BASE FVP_TRUSTED_SRAM_BASE
|
||||
# define TSP_SEC_MEM_SIZE FVP_TRUSTED_SRAM_SIZE
|
||||
# define BL32_BASE FVP_TRUSTED_SRAM_BASE
|
||||
# define BL32_PROGBITS_LIMIT BL2_BASE
|
||||
# define BL32_LIMIT BL31_BASE
|
||||
#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
|
||||
# define TSP_SEC_MEM_BASE TZDRAM_BASE
|
||||
# define TSP_SEC_MEM_SIZE TZDRAM_SIZE
|
||||
# define BL32_BASE (TZDRAM_BASE + 0x2000)
|
||||
# define BL32_LIMIT (TZDRAM_BASE + (1 << 21))
|
||||
#elif FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM
|
||||
# define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE
|
||||
# define TSP_SEC_MEM_SIZE FVP_TRUSTED_DRAM_SIZE
|
||||
# define BL32_BASE (FVP_TRUSTED_DRAM_BASE \
|
||||
+ FVP_SHARED_RAM_SIZE)
|
||||
# define BL32_LIMIT (FVP_TRUSTED_DRAM_BASE + (1 << 21))
|
||||
#else
|
||||
# error "Unsupported TSP_RAM_LOCATION_ID value"
|
||||
# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
|
@ -28,20 +28,37 @@
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
|
||||
# On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
|
||||
# Trusted SRAM is the default.
|
||||
TSP_RAM_LOCATION := tsram
|
||||
|
||||
ifeq (${TSP_RAM_LOCATION}, tsram)
|
||||
TSP_RAM_LOCATION_ID := TSP_IN_TZRAM
|
||||
else ifeq (${TSP_RAM_LOCATION}, tdram)
|
||||
TSP_RAM_LOCATION_ID := TSP_IN_TZDRAM
|
||||
# Shared memory may be allocated at the top of Trusted SRAM (tsram) or at the
|
||||
# base of Trusted SRAM (tdram)
|
||||
FVP_SHARED_DATA_LOCATION := tsram
|
||||
ifeq (${FVP_SHARED_DATA_LOCATION}, tsram)
|
||||
FVP_SHARED_DATA_LOCATION_ID := FVP_IN_TRUSTED_SRAM
|
||||
else ifeq (${FVP_SHARED_DATA_LOCATION}, tdram)
|
||||
FVP_SHARED_DATA_LOCATION_ID := FVP_IN_TRUSTED_DRAM
|
||||
else
|
||||
$(error "Unsupported TSP_RAM_LOCATION value")
|
||||
$(error "Unsupported FVP_SHARED_DATA_LOCATION value")
|
||||
endif
|
||||
|
||||
# Process TSP_RAM_LOCATION_ID flag
|
||||
$(eval $(call add_define,TSP_RAM_LOCATION_ID))
|
||||
# On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
|
||||
# Trusted SRAM is the default.
|
||||
FVP_TSP_RAM_LOCATION := tsram
|
||||
ifeq (${FVP_TSP_RAM_LOCATION}, tsram)
|
||||
FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_SRAM
|
||||
else ifeq (${FVP_TSP_RAM_LOCATION}, tdram)
|
||||
FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_DRAM
|
||||
else
|
||||
$(error "Unsupported FVP_TSP_RAM_LOCATION value")
|
||||
endif
|
||||
|
||||
ifeq (${FVP_SHARED_DATA_LOCATION}, tsram)
|
||||
ifeq (${FVP_TSP_RAM_LOCATION}, tdram)
|
||||
$(error Shared data in Trusted SRAM and TSP in Trusted DRAM is not supported)
|
||||
endif
|
||||
endif
|
||||
|
||||
# Process flags
|
||||
$(eval $(call add_define,FVP_SHARED_DATA_LOCATION_ID))
|
||||
$(eval $(call add_define,FVP_TSP_RAM_LOCATION_ID))
|
||||
|
||||
PLAT_INCLUDES := -Iplat/fvp/include/
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user