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https://github.com/CTCaer/switch-l4t-atf.git
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AArch32: Add generic changes in BL1
This patch adds generic changes in BL1 to support AArch32 state. New AArch32 specific assembly/C files are introduced and some files are moved to AArch32/64 specific folders. BL1 for AArch64 is refactored but functionally identical. BL1 executes in Secure Monitor mode in AArch32 state. NOTE: BL1 in AArch32 state ONLY handles BL1_RUN_IMAGE SMC. Change-Id: I6e2296374c7efbf3cf2aa1a0ce8de0732d8c98a5
This commit is contained in:
Yatharth Kochar
parent
1a0a3f0622
commit
f3b4914be3
38
bl1/aarch32/bl1_arch_setup.c
Normal file
38
bl1/aarch32/bl1_arch_setup.c
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@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
|
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*******************************************************************************
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* TODO: Function that does the first bit of architectural setup.
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******************************************************************************/
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void bl1_arch_setup(void)
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{
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}
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177
bl1/aarch32/bl1_context_mgmt.c
Normal file
177
bl1/aarch32/bl1_context_mgmt.c
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@ -0,0 +1,177 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <context.h>
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#include <context_mgmt.h>
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#include <debug.h>
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#include <platform.h>
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#include <smcc_helpers.h>
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/*
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* Following arrays will be used for context management.
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* There are 2 instances, for the Secure and Non-Secure contexts.
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*/
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static cpu_context_t bl1_cpu_context[2];
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static smc_ctx_t bl1_smc_context[2];
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/* Following contains the next cpu context pointer. */
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static void *bl1_next_cpu_context_ptr;
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/* Following contains the next smc context pointer. */
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static void *bl1_next_smc_context_ptr;
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/* Following functions are used for SMC context handling */
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void *smc_get_ctx(int security_state)
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{
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assert(sec_state_is_valid(security_state));
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return &bl1_smc_context[security_state];
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}
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void smc_set_next_ctx(int security_state)
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{
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assert(sec_state_is_valid(security_state));
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bl1_next_smc_context_ptr = &bl1_smc_context[security_state];
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}
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void *smc_get_next_ctx(void)
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{
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return bl1_next_smc_context_ptr;
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}
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/* Following functions are used for CPU context handling */
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void *cm_get_context(uint32_t security_state)
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{
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assert(sec_state_is_valid(security_state));
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return &bl1_cpu_context[security_state];
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}
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void cm_set_next_context(void *cpu_context)
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{
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assert(cpu_context);
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bl1_next_cpu_context_ptr = cpu_context;
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}
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void *cm_get_next_context(void)
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{
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return bl1_next_cpu_context_ptr;
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}
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/*******************************************************************************
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* Following function copies GP regs r0-r4, lr and spsr,
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* from the CPU context to the SMC context structures.
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******************************************************************************/
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static void copy_cpu_ctx_to_smc_ctx(const regs_t *cpu_reg_ctx,
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smc_ctx_t *next_smc_ctx)
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{
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next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0);
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next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1);
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next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2);
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next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3);
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next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR);
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next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR);
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}
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/*******************************************************************************
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* Following function flushes the SMC & CPU context pointer and its data.
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******************************************************************************/
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static void flush_smc_and_cpu_ctx(void)
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{
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flush_dcache_range((uintptr_t)&bl1_next_smc_context_ptr,
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sizeof(bl1_next_smc_context_ptr));
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flush_dcache_range((uintptr_t)bl1_next_smc_context_ptr,
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sizeof(smc_ctx_t));
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flush_dcache_range((uintptr_t)&bl1_next_cpu_context_ptr,
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sizeof(bl1_next_cpu_context_ptr));
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flush_dcache_range((uintptr_t)bl1_next_cpu_context_ptr,
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sizeof(cpu_context_t));
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}
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/*******************************************************************************
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* This function prepares the context for Secure/Normal world images.
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* Normal world images are transitioned to HYP(if supported) else SVC.
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******************************************************************************/
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void bl1_prepare_next_image(unsigned int image_id)
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{
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unsigned int security_state;
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image_desc_t *image_desc;
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entry_point_info_t *next_bl_ep;
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/* Get the image descriptor. */
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image_desc = bl1_plat_get_image_desc(image_id);
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assert(image_desc);
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/* Get the entry point info. */
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next_bl_ep = &image_desc->ep_info;
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/* Get the image security state. */
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security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
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/* Prepare the SPSR for the next BL image. */
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if (security_state == SECURE) {
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next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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} else {
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/* Use HYP mode if supported else use SVC. */
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if (GET_VIRT_EXT(read_id_pfr1()) == MODE32_hyp) {
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next_bl_ep->spsr = SPSR_MODE32(MODE32_hyp, SPSR_T_ARM,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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} else {
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next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
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SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
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}
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}
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/* Allow platform to make change */
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bl1_plat_set_ep_info(image_id, next_bl_ep);
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/* Prepare the cpu context for the next BL image. */
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cm_init_my_context(next_bl_ep);
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cm_prepare_el3_exit(security_state);
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cm_set_next_context(cm_get_context(security_state));
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/* Prepare the smc context for the next BL image. */
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smc_set_next_ctx(security_state);
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copy_cpu_ctx_to_smc_ctx(get_regs_ctx(cm_get_next_context()),
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smc_get_next_ctx());
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/*
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* Flush the SMC & CPU context and the (next)pointers,
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* to access them after caches are disabled.
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*/
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flush_smc_and_cpu_ctx();
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/* Indicate that image is in execution state. */
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image_desc->state = IMAGE_STATE_EXECUTED;
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print_entry_point_info(next_bl_ep);
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}
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124
bl1/aarch32/bl1_entrypoint.S
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124
bl1/aarch32/bl1_entrypoint.S
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@ -0,0 +1,124 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
|
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
|
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
|
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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#include <context.h>
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#include <el3_common_macros.S>
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#include <smcc_helpers.h>
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#include <smcc_macros.S>
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.globl bl1_vector_table
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.globl bl1_entrypoint
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/* -----------------------------------------------------
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* Setup the vector table to support SVC & MON mode.
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* -----------------------------------------------------
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*/
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vector_base bl1_vector_table
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b bl1_entrypoint
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b report_exception /* Undef */
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b bl1_aarch32_smc_handler /* SMC call */
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b report_exception /* Prefetch abort */
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b report_exception /* Data abort */
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b report_exception /* Reserved */
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b report_exception /* IRQ */
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b report_exception /* FIQ */
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/* -----------------------------------------------------
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* bl1_entrypoint() is the entry point into the trusted
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* firmware code when a cpu is released from warm or
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* cold reset.
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* -----------------------------------------------------
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*/
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func bl1_entrypoint
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/* ---------------------------------------------------------------------
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* If the reset address is programmable then bl1_entrypoint() is
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* executed only on the cold boot path. Therefore, we can skip the warm
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* boot mailbox mechanism.
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* ---------------------------------------------------------------------
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*/
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el3_entrypoint_common \
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_set_endian=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl1_vector_table
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/* -----------------------------------------------------
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* Perform early platform setup & platform
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* specific early arch. setup e.g. mmu setup
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* -----------------------------------------------------
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*/
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bl bl1_early_platform_setup
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bl bl1_plat_arch_setup
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/* -----------------------------------------------------
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* Jump to main function.
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* -----------------------------------------------------
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*/
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bl bl1_main
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/* -----------------------------------------------------
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* Jump to next image.
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* -----------------------------------------------------
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*/
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/*
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* MMU needs to be disabled because both BL1 and BL2 execute
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* in PL1, and therefore share the same address space.
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* BL2 will initialize the address space according to its
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* own requirement.
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*/
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bl disable_mmu_icache_secure
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stcopr r0, TLBIALL
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dsb sy
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isb
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/* Get the cpu_context for next BL image */
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bl cm_get_next_context
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/* Restore the SCR */
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ldr r2, [r0, #CTX_REGS_OFFSET + CTX_SCR]
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stcopr r2, SCR
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isb
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/*
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* Get the smc_context for next BL image,
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* program the gp/system registers and exit
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* secure monitor mode
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*/
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bl smc_get_next_ctx
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smcc_restore_gp_mode_regs
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eret
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endfunc bl1_entrypoint
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96
bl1/aarch32/bl1_exceptions.S
Normal file
96
bl1/aarch32/bl1_exceptions.S
Normal file
@ -0,0 +1,96 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
|
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
* list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
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* Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without specific
|
||||
* prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl1.h>
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#include <bl_common.h>
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.globl bl1_aarch32_smc_handler
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func bl1_aarch32_smc_handler
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/* ------------------------------------------------
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* SMC in BL1 is handled assuming that the MMU is
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* turned off by BL2.
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* ------------------------------------------------
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*/
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/* ----------------------------------------------
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* Only RUN_IMAGE SMC is supported.
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* ----------------------------------------------
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*/
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mov r8, #BL1_SMC_RUN_IMAGE
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cmp r8, r0
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blne report_exception
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/* ------------------------------------------------
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* Make sure only Secure world reaches here.
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* ------------------------------------------------
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*/
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ldcopr r8, SCR
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tst r8, #SCR_NS_BIT
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blne report_exception
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/* ---------------------------------------------------------------------
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* Pass control to next secure image.
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* Here it expects r1 to contain the address of a entry_point_info_t
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* structure describing the BL entrypoint.
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* ---------------------------------------------------------------------
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*/
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mov r8, r1
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mov r0, r1
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bl bl1_print_next_bl_ep_info
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#if SPIN_ON_BL1_EXIT
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bl print_debug_loop_message
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debug_loop:
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b debug_loop
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#endif
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mov r0, r8
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bl bl1_plat_prepare_exit
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stcopr r0, TLBIALL
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dsb sy
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isb
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/*
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* Extract PC and SPSR based on struct `entry_point_info_t`
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* and load it in LR and SPSR registers respectively.
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*/
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ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET]
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ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)]
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msr spsr, r1
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add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET
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ldm r8, {r0, r1, r2, r3}
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eret
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endfunc bl1_aarch32_smc_handler
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@ -192,15 +192,15 @@ func smc_handler64
|
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mov sp, x30
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/* ---------------------------------------------------------------------
|
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* Pass EL3 control to BL31.
|
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* Pass EL3 control to next BL image.
|
||||
* Here it expects X1 with the address of a entry_point_info_t
|
||||
* structure describing the BL31 entrypoint.
|
||||
* structure describing the next BL image entrypoint.
|
||||
* ---------------------------------------------------------------------
|
||||
*/
|
||||
mov x20, x1
|
||||
|
||||
mov x0, x20
|
||||
bl bl1_print_bl31_ep_info
|
||||
bl bl1_print_next_bl_ep_info
|
||||
|
||||
ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
|
||||
msr elr_el3, x0
|
||||
|
||||
18
bl1/bl1.mk
18
bl1/bl1.mk
@ -29,15 +29,19 @@
|
||||
#
|
||||
|
||||
BL1_SOURCES += bl1/bl1_main.c \
|
||||
bl1/aarch64/bl1_arch_setup.c \
|
||||
bl1/aarch64/bl1_entrypoint.S \
|
||||
bl1/aarch64/bl1_exceptions.S \
|
||||
bl1/bl1_context_mgmt.c \
|
||||
lib/cpus/aarch64/cpu_helpers.S \
|
||||
lib/el3_runtime/aarch64/context.S \
|
||||
lib/el3_runtime/aarch64/context_mgmt.c \
|
||||
bl1/${ARCH}/bl1_arch_setup.c \
|
||||
bl1/${ARCH}/bl1_context_mgmt.c \
|
||||
bl1/${ARCH}/bl1_entrypoint.S \
|
||||
bl1/${ARCH}/bl1_exceptions.S \
|
||||
lib/cpus/${ARCH}/cpu_helpers.S \
|
||||
lib/el3_runtime/${ARCH}/context_mgmt.c \
|
||||
plat/common/plat_bl1_common.c
|
||||
|
||||
|
||||
ifeq (${ARCH},aarch64)
|
||||
BL1_SOURCES += lib/el3_runtime/aarch64/context.S
|
||||
endif
|
||||
|
||||
ifeq (${TRUSTED_BOARD_BOOT},1)
|
||||
BL1_SOURCES += bl1/bl1_fwu.c
|
||||
endif
|
||||
|
||||
@ -107,15 +107,20 @@ void bl1_main(void)
|
||||
NOTICE("BL1: %s\n", version_string);
|
||||
NOTICE("BL1: %s\n", build_message);
|
||||
|
||||
INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT);
|
||||
INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE,
|
||||
(void *)BL1_RAM_LIMIT);
|
||||
|
||||
|
||||
#if DEBUG
|
||||
unsigned long val;
|
||||
u_register_t val;
|
||||
/*
|
||||
* Ensure that MMU/Caches and coherency are turned on
|
||||
*/
|
||||
#ifdef AARCH32
|
||||
val = read_sctlr();
|
||||
#else
|
||||
val = read_sctlr_el3();
|
||||
#endif
|
||||
assert(val & SCTLR_M_BIT);
|
||||
assert(val & SCTLR_C_BIT);
|
||||
assert(val & SCTLR_I_BIT);
|
||||
@ -223,21 +228,25 @@ void bl1_load_bl2(void)
|
||||
|
||||
bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
|
||||
|
||||
ep_info->args.arg1 = (unsigned long)bl2_tzram_layout;
|
||||
ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout;
|
||||
NOTICE("BL1: Booting BL2\n");
|
||||
VERBOSE("BL1: BL2 memory layout address = 0x%llx\n",
|
||||
(unsigned long long) bl2_tzram_layout);
|
||||
VERBOSE("BL1: BL2 memory layout address = %p\n",
|
||||
(void *) bl2_tzram_layout);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Function called just before handing over to BL31 to inform the user about
|
||||
* the boot progress. In debug mode, also print details about the BL31 image's
|
||||
* execution context.
|
||||
* Function called just before handing over to the next BL to inform the user
|
||||
* about the boot progress. In debug mode, also print details about the BL
|
||||
* image's execution context.
|
||||
******************************************************************************/
|
||||
void bl1_print_bl31_ep_info(const entry_point_info_t *bl31_ep_info)
|
||||
void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
|
||||
{
|
||||
#ifdef AARCH32
|
||||
NOTICE("BL1: Booting BL32\n");
|
||||
#else
|
||||
NOTICE("BL1: Booting BL31\n");
|
||||
print_entry_point_info(bl31_ep_info);
|
||||
#endif /* AARCH32 */
|
||||
print_entry_point_info(bl_ep_info);
|
||||
}
|
||||
|
||||
#if SPIN_ON_BL1_EXIT
|
||||
|
||||
@ -37,13 +37,13 @@
|
||||
* Declarations of linker defined symbols which will tell us where BL1 lives
|
||||
* in Trusted ROM and RAM
|
||||
******************************************************************************/
|
||||
extern uint64_t __BL1_ROM_END__;
|
||||
#define BL1_ROM_END (uint64_t)(&__BL1_ROM_END__)
|
||||
extern uintptr_t __BL1_ROM_END__;
|
||||
#define BL1_ROM_END (uintptr_t)(&__BL1_ROM_END__)
|
||||
|
||||
extern uint64_t __BL1_RAM_START__;
|
||||
extern uint64_t __BL1_RAM_END__;
|
||||
#define BL1_RAM_BASE (uint64_t)(&__BL1_RAM_START__)
|
||||
#define BL1_RAM_LIMIT (uint64_t)(&__BL1_RAM_END__)
|
||||
extern uintptr_t __BL1_RAM_START__;
|
||||
extern uintptr_t __BL1_RAM_END__;
|
||||
#define BL1_RAM_BASE (uintptr_t)(&__BL1_RAM_START__)
|
||||
#define BL1_RAM_LIMIT (uintptr_t)(&__BL1_RAM_END__)
|
||||
|
||||
/******************************************
|
||||
* Function prototypes
|
||||
|
||||
@ -103,5 +103,9 @@ static inline void cm_set_next_context(void *context)
|
||||
"msr spsel, #0\n"
|
||||
: : "r" (context));
|
||||
}
|
||||
|
||||
#else
|
||||
void *cm_get_next_context(void);
|
||||
#endif /* AARCH32 */
|
||||
|
||||
#endif /* __CM_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user