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https://github.com/CTCaer/switch-l4t-atf.git
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Merge pull request #1232 from masahir0y/uniphier
uniphier: migrate to BL2-AT-EL3
This commit is contained in:
davidcunado-arm
GitHub
commit
f478253da8
@ -3,26 +3,28 @@ ARM Trusted Firmware for Socionext UniPhier SoCs
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Socionext UniPhier ARMv8-A SoCs use ARM Trusted Firmware as the secure world
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firmware, supporting BL1, BL2, and BL31.
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firmware, supporting BL2 and BL31.
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UniPhier SoC family implements its internal boot ROM, so BL1 is used as pseudo
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ROM (i.e. runs in RAM). The internal boot ROM loads 64KB [1]_ image from a
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non-volatile storage to the on-chip SRAM. Unfortunately, BL1 does not fit in
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the 64KB limit if `Trusted Board Boot`_ (TBB) is enabled. To solve this problem,
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Socionext provides a first stage loader called `UniPhier BL`_. This loader runs
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in the on-chip SRAM, initializes the DRAM, expands BL1 there, and hands the
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control over to it. Therefore, all images of ARM Trusted Firmware run in DRAM.
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UniPhier SoC family implements its internal boot ROM, which loads 64KB [1]_
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image from a non-volatile storage to the on-chip SRAM, and jumps over to it.
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ARM Trusted Firmware provides a special mode, BL2-AT-EL3, which enables BL2 to
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execute at EL3. It is useful for platforms with non-TF boot ROM, like UniPhier.
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Here, a problem is BL2 does not fit in the 64KB limit if `Trusted Board Boot`_
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(TBB) is enabled. To solve this issue, Socionext provides a first stage loader
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called `UniPhier BL`_. This loader runs in the on-chip SRAM, initializes the
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DRAM, expands BL2 there, and hands the control over to it. Therefore, all images
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of ARM Trusted Firmware run in DRAM.
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The UniPhier platform works with/without TBB. See below for the build process
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of each case. The image authentication for the UniPhier platform fully
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complies with the Trusted Board Boot Requirements (TBBR) specification.
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The UniPhier BL does not implement the authentication functionality, that is,
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it can not verify the BL1 image by itself. Instead, the UniPhier BL assures
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the BL1 validity in a different way; BL1 is GZIP-compressed and appended to
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the UniPhier BL. The concatenation of the UniPhier BL and the compressed BL1
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fits in the 64KB limit. The concatenated image is loaded by the boot ROM
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(and verified if the chip fuses are blown).
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it can not verify the BL2 image by itself. Instead, the UniPhier BL assures
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the BL2 validity in a different way; BL2 is GZIP-compressed and appended to
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the UniPhier BL. The concatenation of the UniPhier BL and the compressed BL2
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fits in the 64KB limit. The concatenated image is loaded by the internal boot
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ROM (and verified if the chip fuses are blown).
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Boot Flow
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@ -31,32 +33,32 @@ Boot Flow
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1. The Boot ROM
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This is hard-wired ROM, so never corrupted. It loads the UniPhier BL (with
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compressed-BL1 appended) into the on-chip SRAM. If the SoC fuses are blown,
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compressed-BL2 appended) into the on-chip SRAM. If the SoC fuses are blown,
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the image is verified by the SoC's own method.
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2. UniPhier BL
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This runs in the on-chip SRAM. After the minimum SoC initialization and DRAM
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setup, it decompresses the appended BL1 image into the DRAM, then jumps to
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the BL1 entry.
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setup, it decompresses the appended BL2 image into the DRAM, then jumps to
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the BL2 entry.
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3. BL1
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3. BL2 (at EL3)
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This runs in the DRAM. It extracts BL2 from FIP (Firmware Image Package).
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If TBB is enabled, the BL2 is authenticated by the standard mechanism of ARM
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Trusted Firmware.
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This runs in the DRAM. It extracts more images such as BL31, BL33 (optionally
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SCP_BL2, BL32 as well) from Firmware Image Package (FIP). If TBB is enabled,
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they are all authenticated by the standard mechanism of ARM Trusted Firmware.
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After loading all the images, it jumps to the BL31 entry.
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4. BL2, BL31, and more
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4. BL31, BL32, and BL33
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They all run in the DRAM, and are authenticated by the standard mechanism if
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TBB is enabled. See `Firmware Design`_ for details.
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They all run in the DRAM. See `Firmware Design`_ for details.
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Basic Build
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-----------
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BL1 must be compressed for the reason above. The UniPhier's platform makefile
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provides a build target ``bl1_gzip`` for this.
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BL2 must be compressed for the reason above. The UniPhier's platform makefile
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provides a build target ``bl2_gzip`` for this.
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For a non-secure boot loader (aka BL33), U-Boot is well supported for UniPhier
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SoCs. The U-Boot image (``u-boot.bin``) must be built in advance. For the build
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@ -64,11 +66,11 @@ procedure of U-Boot, refer to the document in the `U-Boot`_ project.
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To build minimum functionality for UniPhier (without TBB)::
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make CROSS_COMPILE=<gcc-prefix> PLAT=uniphier BL33=<path-to-BL33> bl1_gzip fip
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make CROSS_COMPILE=<gcc-prefix> PLAT=uniphier BL33=<path-to-BL33> bl2_gzip fip
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Output images:
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- ``bl1.bin.gzip``
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- ``bl2.bin.gz``
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- ``fip.bin``
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -27,29 +27,20 @@
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#define PLAT_MAX_OFF_STATE 2
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#define PLAT_MAX_RET_STATE 1
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#define UNIPHIER_SEC_DRAM_BASE 0x81000000
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#define UNIPHIER_SEC_DRAM_BASE 0x80000000
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#define UNIPHIER_SEC_DRAM_LIMIT 0x82000000
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#define UNIPHIER_SEC_DRAM_SIZE ((UNIPHIER_SEC_DRAM_LIMIT) - \
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(UNIPHIER_SEC_DRAM_BASE))
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#define BL1_RO_BASE 0x80000000
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#define BL1_RO_LIMIT 0x80018000
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#define BL1_RW_LIMIT (UNIPHIER_SEC_DRAM_LIMIT)
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#define BL1_RW_BASE ((BL1_RW_LIMIT) - 0x00040000)
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#define BL2_BASE (UNIPHIER_SEC_DRAM_BASE)
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#define BL2_LIMIT ((BL2_BASE) + 0x00020000)
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#define BL2_LIMIT (BL1_RW_BASE)
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#define BL2_BASE ((BL2_LIMIT) - 0x00040000)
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#define BL31_BASE (UNIPHIER_SEC_DRAM_BASE)
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#define BL31_BASE (BL2_LIMIT)
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#define BL31_LIMIT ((BL31_BASE) + 0x00080000)
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#define BL32_BASE (BL31_LIMIT)
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#define BL32_LIMIT (UNIPHIER_SEC_DRAM_LIMIT)
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#define UNIPHIER_BLOCK_BUF_SIZE 0x00400000
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#define UNIPHIER_BLOCK_BUF_BASE ((BL2_BASE) - \
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(UNIPHIER_BLOCK_BUF_SIZE))
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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@ -63,7 +54,6 @@
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#define TSP_SEC_MEM_BASE (BL32_BASE)
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#define TSP_SEC_MEM_SIZE ((BL32_LIMIT) - (BL32_BASE))
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#define TSP_PROGBITS_LIMIT (UNIPHIER_BLOCK_BUF_BASE)
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#define TSP_IRQ_SEC_PHY_TIMER 29
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#endif /* __PLATFORM_DEF_H__ */
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@ -1,15 +1,17 @@
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#
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# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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override COLD_BOOT_SINGLE_CPU := 1
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override ENABLE_PLAT_COMPAT := 0
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override LOAD_IMAGE_V2 := 1
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override USE_COHERENT_MEM := 1
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override USE_TBBR_DEFS := 1
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override ENABLE_SVE_FOR_NS := 0
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override BL2_AT_EL3 := 1
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override COLD_BOOT_SINGLE_CPU := 1
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override ENABLE_PLAT_COMPAT := 0
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override LOAD_IMAGE_V2 := 1
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override PROGRAMMABLE_RESET_ADDRESS := 1
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override USE_COHERENT_MEM := 1
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override USE_TBBR_DEFS := 1
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override ENABLE_SVE_FOR_NS := 0
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# Cortex-A53 revision r0p4-51rel0
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# needed for LD20, unneeded for LD11, PXs3 (no ACE)
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@ -27,18 +29,7 @@ include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_PATH := plat/socionext/uniphier
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PLAT_INCLUDES := -I$(PLAT_PATH)/include
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# IO sources for BL1, BL2
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IO_SOURCES := drivers/io/io_block.c \
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drivers/io/io_fip.c \
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drivers/io/io_memmap.c \
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drivers/io/io_storage.c \
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$(PLAT_PATH)/uniphier_boot_device.c \
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$(PLAT_PATH)/uniphier_emmc.c \
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$(PLAT_PATH)/uniphier_io_storage.c \
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$(PLAT_PATH)/uniphier_nand.c \
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$(PLAT_PATH)/uniphier_usb.c
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# common sources for BL1, BL2, BL31
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# common sources for BL2, BL31 (and BL32 if SPD=tspd)
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PLAT_BL_COMMON_SOURCES += drivers/console/aarch64/console.S \
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$(PLAT_PATH)/uniphier_console.S \
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$(PLAT_PATH)/uniphier_helpers.S \
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@ -46,17 +37,21 @@ PLAT_BL_COMMON_SOURCES += drivers/console/aarch64/console.S \
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$(PLAT_PATH)/uniphier_xlat_setup.c \
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${XLAT_TABLES_LIB_SRCS}
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BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a72.S \
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$(PLAT_PATH)/uniphier_bl1_helpers.S \
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$(PLAT_PATH)/uniphier_bl1_setup.c \
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$(IO_SOURCES)
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BL2_SOURCES += common/desc_image_load.c \
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drivers/io/io_block.c \
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drivers/io/io_fip.c \
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drivers/io/io_memmap.c \
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drivers/io/io_storage.c \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a72.S \
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$(PLAT_PATH)/uniphier_bl2_setup.c \
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$(PLAT_PATH)/uniphier_boot_device.c \
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$(PLAT_PATH)/uniphier_emmc.c \
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$(PLAT_PATH)/uniphier_image_desc.c \
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$(PLAT_PATH)/uniphier_io_storage.c \
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$(PLAT_PATH)/uniphier_nand.c \
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$(PLAT_PATH)/uniphier_scp.c \
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$(IO_SOURCES)
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$(PLAT_PATH)/uniphier_usb.c
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BL31_SOURCES += drivers/arm/cci/cci.c \
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drivers/arm/gic/common/gic_common.c \
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@ -82,7 +77,7 @@ include drivers/auth/mbedtls/mbedtls_x509.mk
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PLAT_INCLUDES += -Iinclude/common/tbbr
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TBB_SOURCES := drivers/auth/auth_mod.c \
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BL2_SOURCES += drivers/auth/auth_mod.c \
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drivers/auth/crypto_mod.c \
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drivers/auth/img_parser_mod.c \
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drivers/auth/tbbr/tbbr_cot.c \
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@ -90,14 +85,10 @@ TBB_SOURCES := drivers/auth/auth_mod.c \
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$(PLAT_PATH)/uniphier_rotpk.S \
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$(PLAT_PATH)/uniphier_tbbr.c
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BL1_SOURCES += $(TBB_SOURCES)
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BL2_SOURCES += $(TBB_SOURCES)
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ROT_KEY = $(BUILD_PLAT)/rot_key.pem
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ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
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$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
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$(BUILD_PLAT)/bl1/uniphier_rotpk.o: $(ROTPK_HASH)
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$(BUILD_PLAT)/bl2/uniphier_rotpk.o: $(ROTPK_HASH)
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certificates: $(ROT_KEY)
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@ -112,8 +103,8 @@ $(ROTPK_HASH): $(ROT_KEY)
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endif
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.PHONY: bl1_gzip
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bl1_gzip: $(BUILD_PLAT)/bl1.bin.gzip
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%.gzip: %
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.PHONY: bl2_gzip
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bl2_gzip: $(BUILD_PLAT)/bl2.bin.gz
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%.gz: %
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@echo " GZIP $@"
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$(Q)gzip -n -f -9 $< --stdout > $@
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -67,7 +67,9 @@ void uniphier_gic_pcpu_init(void);
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unsigned int uniphier_calc_core_pos(u_register_t mpidr);
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#define UNIPHIER_NS_DRAM_BASE 0x84000000
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#define UNIPHIER_NS_DRAM_SIZE 0x01000000
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#define UNIPHIER_NS_DRAM_LIMIT 0x85000000
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#define UNIPHIER_NS_DRAM_SIZE ((UNIPHIER_NS_DRAM_LIMIT) - \
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(UNIPHIER_NS_DRAM_BASE))
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#define UNIPHIER_BL33_BASE (UNIPHIER_NS_DRAM_BASE)
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#define UNIPHIER_BL33_MAX_SIZE 0x00100000
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@ -76,4 +78,9 @@ unsigned int uniphier_calc_core_pos(u_register_t mpidr);
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(UNIPHIER_BL33_MAX_SIZE))
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#define UNIPHIER_SCP_MAX_SIZE 0x00020000
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#define UNIPHIER_BLOCK_BUF_BASE ((UNIPHIER_SCP_BASE) + \
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(UNIPHIER_SCP_MAX_SIZE))
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#define UNIPHIER_BLOCK_BUF_SIZE ((UNIPHIER_NS_DRAM_LIMIT) - \
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(UNIPHIER_BLOCK_BUF_BASE))
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#endif /* __UNIPHIER_H__ */
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@ -1,15 +0,0 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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.globl plat_get_my_entrypoint
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func plat_get_my_entrypoint
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mov x0, #0
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ret
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endfunc plat_get_my_entrypoint
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@ -1,56 +0,0 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <bl_common.h>
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#include <console.h>
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#include <debug.h>
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#include <errno.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <xlat_mmu_helpers.h>
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#include "uniphier.h"
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void bl1_early_platform_setup(void)
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{
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uniphier_console_setup();
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}
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void bl1_plat_arch_setup(void)
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{
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uniphier_mmap_setup(UNIPHIER_SEC_DRAM_BASE, UNIPHIER_SEC_DRAM_SIZE,
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NULL);
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enable_mmu_el3(0);
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}
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void bl1_platform_setup(void)
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{
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unsigned int soc;
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int ret;
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soc = uniphier_get_soc_id();
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if (soc == UNIPHIER_SOC_UNKNOWN) {
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ERROR("unsupported SoC\n");
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plat_error_handler(-ENOTSUP);
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}
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ret = uniphier_io_setup(soc);
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if (ret) {
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ERROR("failed to setup io devices\n");
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plat_error_handler(ret);
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}
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}
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static meminfo_t uniphier_tzram_layout = {
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.total_base = UNIPHIER_SEC_DRAM_BASE,
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.total_size = UNIPHIER_SEC_DRAM_SIZE,
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};
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meminfo_t *bl1_plat_sec_mem_layout(void)
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{
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return &uniphier_tzram_layout;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -15,13 +15,11 @@
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#include "uniphier.h"
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static meminfo_t uniphier_bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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static int uniphier_bl2_kick_scp;
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void bl2_early_platform_setup(meminfo_t *mem_layout)
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void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
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u_register_t x2, u_register_t x3)
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{
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uniphier_bl2_tzram_layout = *mem_layout;
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uniphier_console_setup();
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}
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@ -32,7 +30,7 @@ static const struct mmap_region uniphier_bl2_mmap[] = {
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{ .size = 0 },
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};
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void bl2_plat_arch_setup(void)
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void bl2_el3_plat_arch_setup(void)
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{
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unsigned int soc;
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int skip_scp = 0;
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@ -40,7 +38,7 @@ void bl2_plat_arch_setup(void)
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uniphier_mmap_setup(UNIPHIER_SEC_DRAM_BASE, UNIPHIER_SEC_DRAM_SIZE,
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uniphier_bl2_mmap);
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enable_mmu_el1(0);
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enable_mmu_el3(0);
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soc = uniphier_get_soc_id();
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if (soc == UNIPHIER_SOC_UNKNOWN) {
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