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https://github.com/CTCaer/switch-l4t-atf.git
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Demonstrate model for routing IRQs to EL3
This patch provides an option to specify a interrupt routing model where non-secure interrupts (IRQs) are routed to EL3 instead of S-EL1. When such an interrupt occurs, the TSPD arranges a return to the normal world after saving any necessary context. The interrupt routing model to route IRQs to EL3 is enabled only during STD SMC processing. Thus the pre-emption of S-EL1 is disabled during Fast SMC and Secure Interrupt processing. A new build option TSPD_ROUTE_NS_INT_EL3 is introduced to change the non secure interrupt target execution level to EL3. Fixes ARM-software/tf-issues#225 Change-Id: Ia1e779fbbb6d627091e665c73fa6315637cfdd32
This commit is contained in:
Soby Mathew
parent
07ddb33a8e
commit
f4f1ae777b
@ -158,6 +158,45 @@ int32_t set_routing_model(uint32_t type, uint32_t flags)
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return 0;
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}
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/******************************************************************************
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* This function disables the routing model of interrupt 'type' from the
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* specified 'security_state' on the local core. The disable is in effect
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* till the core powers down or till the next enable for that interrupt
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* type.
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*****************************************************************************/
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int disable_intr_rm_local(uint32_t type, uint32_t security_state)
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{
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uint32_t bit_pos, flag;
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assert(intr_type_descs[type].handler);
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flag = get_interrupt_rm_flag(INTR_DEFAULT_RM, security_state);
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bit_pos = plat_interrupt_type_to_line(type, security_state);
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cm_write_scr_el3_bit(security_state, bit_pos, flag);
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return 0;
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}
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/******************************************************************************
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* This function enables the routing model of interrupt 'type' from the
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* specified 'security_state' on the local core.
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*****************************************************************************/
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int enable_intr_rm_local(uint32_t type, uint32_t security_state)
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{
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uint32_t bit_pos, flag;
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assert(intr_type_descs[type].handler);
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flag = get_interrupt_rm_flag(intr_type_descs[type].flags,
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security_state);
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bit_pos = plat_interrupt_type_to_line(type, security_state);
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cm_write_scr_el3_bit(security_state, bit_pos, flag);
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return 0;
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}
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/*******************************************************************************
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* This function registers a handler for the 'type' of interrupt specified. It
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* also validates the routing model specified in the 'flags' for this type of
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@ -251,6 +251,11 @@ performed.
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(Coherent memory region is included) or 0 (Coherent memory region is
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excluded). Default is 1.
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* `TSPD_ROUTE_IRQ_TO_EL3`: A non zero value enables the routing model
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for non-secure interrupts in which they are routed to EL3 (TSPD). The
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default model (when the value is 0) is to route non-secure interrupts
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to S-EL1 (TSP).
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#### FVP specific build options
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* `FVP_TSP_RAM_LOCATION`: location of the TSP binary. Options:
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@ -63,7 +63,8 @@
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#define INTR_NS_VALID_RM0 0x0
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/* Routed to EL1/EL2 from NS and to EL3 from Secure */
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#define INTR_NS_VALID_RM1 0x1
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/* This is the default routing model */
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#define INTR_DEFAULT_RM 0x0
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/*******************************************************************************
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* Constants for the _individual_ routing model bits in the 'flags' field for
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@ -123,6 +124,8 @@ int32_t register_interrupt_type_handler(uint32_t type,
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interrupt_type_handler_t handler,
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uint32_t flags);
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interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type);
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int disable_intr_rm_local(uint32_t type, uint32_t security_state);
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int enable_intr_rm_local(uint32_t type, uint32_t security_state);
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#endif /*__ASSEMBLY__*/
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#endif /* __INTERRUPT_MGMT_H__ */
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@ -52,3 +52,10 @@ include ${BL32_ROOT}/tsp.mk
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# Let the top-level Makefile know that we intend to build the SP from source
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NEED_BL32 := yes
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# Flag used to enable routing of non-secure interrupts to EL3 when they are
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# generated while the code is executing in S-EL1/0.
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TSPD_ROUTE_IRQ_TO_EL3 := 0
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$(eval $(call assert_boolean,TSPD_ROUTE_IRQ_TO_EL3))
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$(eval $(call add_define,TSPD_ROUTE_IRQ_TO_EL3))
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@ -48,6 +48,7 @@
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#include <platform.h>
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#include <runtime_svc.h>
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#include <stddef.h>
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#include <string.h>
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#include <tsp.h>
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#include <uuid.h>
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#include "tspd_private.h"
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@ -71,6 +72,24 @@ DEFINE_SVC_UUID(tsp_uuid,
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int32_t tspd_init(void);
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uint64_t tspd_handle_sp_preemption(void *handle)
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{
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cpu_context_t *ns_cpu_context;
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assert(handle == cm_get_context(SECURE));
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cm_el1_sysregs_context_save(SECURE);
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/* Get a reference to the non-secure context */
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ns_cpu_context = cm_get_context(NON_SECURE);
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assert(ns_cpu_context);
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/*
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* Restore non-secure state. The secure system
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* register context will be saved when required.
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*/
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cm_el1_sysregs_context_restore(NON_SECURE);
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cm_set_next_eret_context(NON_SECURE);
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SMC_RET1(ns_cpu_context, SMC_PREEMPTED);
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}
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/*******************************************************************************
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* This function is the handler registered for S-EL1 interrupts by the TSPD. It
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* validates the interrupt and upon success arranges entry into the TSP at
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@ -120,11 +139,16 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
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CTX_SPSR_EL3);
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tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx,
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CTX_ELR_EL3);
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#if TSPD_ROUTE_IRQ_TO_EL3
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/*Need to save the previously interrupted secure context */
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memcpy(&tsp_ctx->sp_ctx, &tsp_ctx->cpu_ctx, TSPD_SP_CTX_SIZE);
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#endif
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}
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cm_el1_sysregs_context_restore(SECURE);
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cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->fiq_entry,
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SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS));
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cm_set_next_eret_context(SECURE);
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/*
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@ -137,6 +161,34 @@ static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
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SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_FIQ_AND_RETURN, read_elr_el3());
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}
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#if TSPD_ROUTE_IRQ_TO_EL3
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/*******************************************************************************
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* This function is the handler registered for S-EL1 interrupts by the TSPD. It
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* validates the interrupt and upon success arranges entry into the TSP at
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* 'tsp_fiq_entry()' for handling the interrupt.
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******************************************************************************/
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static uint64_t tspd_ns_interrupt_handler(uint32_t id,
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uint32_t flags,
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void *handle,
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void *cookie)
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{
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/* Check the security state when the exception was generated */
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assert(get_interrupt_src_ss(flags) == SECURE);
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#if IMF_READ_INTERRUPT_ID
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/* Check the security status of the interrupt */
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assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_NS);
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#endif
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/*
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* Disable the routing of NS interrupts from secure world to EL3 while
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* interrupted on this core.
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*/
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disable_intr_rm_local(INTR_TYPE_NS, SECURE);
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return tspd_handle_sp_preemption(handle);
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}
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#endif
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/*******************************************************************************
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* Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type
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* (aarch32/aarch64) if not already known and initialises the context for entry
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@ -270,21 +322,7 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
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if (ns)
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SMC_RET1(handle, SMC_UNK);
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assert(handle == cm_get_context(SECURE));
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cm_el1_sysregs_context_save(SECURE);
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/* Get a reference to the non-secure context */
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ns_cpu_context = cm_get_context(NON_SECURE);
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assert(ns_cpu_context);
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/*
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* Restore non-secure state. There is no need to save the
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* secure system register context since the TSP was supposed
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* to preserve it during S-EL1 interrupt handling.
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*/
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cm_el1_sysregs_context_restore(NON_SECURE);
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cm_set_next_eret_context(NON_SECURE);
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SMC_RET1(ns_cpu_context, SMC_PREEMPTED);
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return tspd_handle_sp_preemption(handle);
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/*
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* This function ID is used only by the TSP to indicate that it has
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@ -308,6 +346,14 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
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SMC_SET_EL3(&tsp_ctx->cpu_ctx,
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CTX_ELR_EL3,
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tsp_ctx->saved_elr_el3);
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#if TSPD_ROUTE_IRQ_TO_EL3
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/*
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* Need to restore the previously interrupted
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* secure context.
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*/
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memcpy(&tsp_ctx->cpu_ctx, &tsp_ctx->sp_ctx,
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TSPD_SP_CTX_SIZE);
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#endif
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}
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/* Get a reference to the non-secure context */
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@ -389,6 +435,28 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
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flags);
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if (rc)
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panic();
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#if TSPD_ROUTE_IRQ_TO_EL3
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/*
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* Register an interrupt handler for NS interrupts when
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* generated during code executing in secure state are
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* routed to EL3.
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*/
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flags = 0;
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set_interrupt_rm_flag(flags, SECURE);
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rc = register_interrupt_type_handler(INTR_TYPE_NS,
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tspd_ns_interrupt_handler,
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flags);
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if (rc)
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panic();
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/*
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* Disable the interrupt NS locally since it will be enabled globally
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* within cm_init_context.
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*/
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disable_intr_rm_local(INTR_TYPE_NS, SECURE);
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#endif
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}
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@ -507,6 +575,13 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
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set_std_smc_active_flag(tsp_ctx->state);
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cm_set_elr_el3(SECURE, (uint64_t)
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&tsp_vectors->std_smc_entry);
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#if TSPD_ROUTE_IRQ_TO_EL3
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/*
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* Enable the routing of NS interrupts to EL3
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* during STD SMC processing on this core.
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*/
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enable_intr_rm_local(INTR_TYPE_NS, SECURE);
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#endif
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}
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cm_el1_sysregs_context_restore(SECURE);
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@ -529,8 +604,18 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
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/* Restore non-secure state */
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cm_el1_sysregs_context_restore(NON_SECURE);
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cm_set_next_eret_context(NON_SECURE);
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if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_STD)
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if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_STD) {
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clr_std_smc_active_flag(tsp_ctx->state);
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#if TSPD_ROUTE_IRQ_TO_EL3
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/*
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* Disable the routing of NS interrupts to EL3
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* after STD SMC processing is finished on this
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* core.
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*/
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disable_intr_rm_local(INTR_TYPE_NS, SECURE);
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#endif
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}
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SMC_RET3(ns_cpu_context, x1, x2, x3);
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}
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@ -564,6 +649,15 @@ uint64_t tspd_smc_handler(uint32_t smc_fid,
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* We are done stashing the non-secure context. Ask the
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* secure payload to do the work now.
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*/
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#if TSPD_ROUTE_IRQ_TO_EL3
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/*
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* Enable the routing of NS interrupts to EL3 during resumption
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* of STD SMC call on this core.
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*/
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enable_intr_rm_local(INTR_TYPE_NS, SECURE);
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#endif
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/* We just need to return to the preempted point in
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* TSP and the execution will resume as normal.
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@ -133,6 +133,14 @@ static void tspd_cpu_on_finish_handler(uint64_t unused)
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/* Initialise this cpu's secure context */
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cm_init_context(mpidr, &tsp_on_entrypoint);
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#if TSPD_ROUTE_IRQ_TO_EL3
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/*
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* Disable the NS interrupt locally since it will be enabled globally
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* within cm_init_context.
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*/
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disable_intr_rm_local(INTR_TYPE_NS, SECURE);
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#endif
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/* Enter the TSP */
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rc = tspd_synchronous_sp_entry(tsp_ctx);
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@ -120,6 +120,34 @@
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#define TSPD_C_RT_CTX_SIZE 0x60
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#define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT)
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/*******************************************************************************
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* Constants that allow assembler code to preserve caller-saved registers of the
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* SP context while performing a TSP preemption.
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* Note: These offsets have to match with the offsets for the corresponding
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* registers in cpu_context as we are using memcpy to copy the values from
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* cpu_context to sp_ctx.
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******************************************************************************/
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#define TSPD_SP_CTX_X0 0x0
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#define TSPD_SP_CTX_X1 0x8
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#define TSPD_SP_CTX_X2 0x10
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#define TSPD_SP_CTX_X3 0x18
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#define TSPD_SP_CTX_X4 0x20
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#define TSPD_SP_CTX_X5 0x28
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#define TSPD_SP_CTX_X6 0x30
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#define TSPD_SP_CTX_X7 0x38
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#define TSPD_SP_CTX_X8 0x40
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#define TSPD_SP_CTX_X9 0x48
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#define TSPD_SP_CTX_X10 0x50
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#define TSPD_SP_CTX_X11 0x58
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#define TSPD_SP_CTX_X12 0x60
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#define TSPD_SP_CTX_X13 0x68
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#define TSPD_SP_CTX_X14 0x70
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#define TSPD_SP_CTX_X15 0x78
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#define TSPD_SP_CTX_X16 0x80
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#define TSPD_SP_CTX_X17 0x88
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#define TSPD_SP_CTX_SIZE 0x90
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#define TSPD_SP_CTX_ENTRIES (TSPD_SP_CTX_SIZE >> DWORD_SHIFT)
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#ifndef __ASSEMBLY__
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#include <cassert.h>
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@ -142,6 +170,17 @@ DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES);
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CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \
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assert_spd_c_rt_regs_size_mismatch);
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/* SEL1 Secure payload (SP) caller saved register context structure. */
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DEFINE_REG_STRUCT(sp_ctx_regs, TSPD_SP_CTX_ENTRIES);
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/*
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* Compile time assertion to ensure that both the compiler and linker
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* have the same double word aligned view of the size of the C runtime
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* register context.
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*/
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CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t), \
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assert_spd_sp_regs_size_mismatch);
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/*******************************************************************************
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* Structure which helps the SPD to maintain the per-cpu state of the SP.
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* 'saved_spsr_el3' - temporary copy to allow FIQ handling when the TSP has been
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@ -155,6 +194,10 @@ CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \
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* 'cpu_ctx' - space to maintain SP architectural state
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* 'saved_tsp_args' - space to store arguments for TSP arithmetic operations
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* which will queried using the TSP_GET_ARGS SMC by TSP.
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* 'sp_ctx' - space to save the SEL1 Secure Payload(SP) caller saved
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* register context after it has been preempted by an EL3
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* routed NS interrupt and when a Secure Interrupt is taken
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* to SP.
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******************************************************************************/
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typedef struct tsp_context {
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uint64_t saved_elr_el3;
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@ -164,6 +207,9 @@ typedef struct tsp_context {
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uint64_t c_rt_ctx;
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cpu_context_t cpu_ctx;
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uint64_t saved_tsp_args[TSP_NUM_ARGS];
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#if TSPD_ROUTE_IRQ_TO_EL3
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sp_ctx_regs_t sp_ctx;
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#endif
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} tsp_context_t;
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/* Helper macros to store and retrieve tsp args from tsp_context */
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