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https://github.com/CTCaer/switch-l4t-atf.git
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gic/gic600: add support for multichip configuration
Add support to configure GIC-600's multichip routing table registers. Introduce a new gic600 multichip structure in order to support platforms to pass their GIC-600 multichip information such as routing table owner, SPI blocks ownership. This driver is currently experimental and the driver api may change in the future. Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
This commit is contained in:
Vijayenthiran Subramaniam
parent
74c2124400
commit
fcc337cf49
240
drivers/arm/gic/v3/gic600_multichip.c
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240
drivers/arm/gic/v3/gic600_multichip.c
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@ -0,0 +1,240 @@
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/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* GIC-600 driver extension for multichip setup
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*/
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#include <assert.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv3.h>
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#include <drivers/arm/gic600_multichip.h>
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#include "gic600_multichip_private.h"
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#include "../common/gic_common_private.h"
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#warning "GIC-600 Multichip driver is currently experimental and the API may change in future."
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/*******************************************************************************
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* GIC-600 multichip operation related helper functions
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******************************************************************************/
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static void gicd_dchipr_wait_for_power_update_progress(uintptr_t base)
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{
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unsigned int retry = GICD_PUP_UPDATE_RETRIES;
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while ((read_gicd_dchipr(base) & GICD_DCHIPR_PUP_BIT) != 0U) {
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if (retry-- == 0) {
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ERROR("GIC-600 connection to Routing Table Owner timed "
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"out\n");
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panic();
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}
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}
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}
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/*******************************************************************************
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* Sets up the routing table owner.
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******************************************************************************/
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static void set_gicd_dchipr_rt_owner(uintptr_t base, unsigned int rt_owner)
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{
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/*
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* Ensure that Group enables in GICD_CTLR are disabled and no pending
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* register writes to GICD_CTLR.
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*/
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if ((gicd_read_ctlr(base) &
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(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT |
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CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) {
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ERROR("GICD_CTLR group interrupts are either enabled or have "
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"pending writes. Cannot set RT owner.\n");
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panic();
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}
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/* Poll till PUP is zero before intiating write */
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gicd_dchipr_wait_for_power_update_progress(base);
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write_gicd_dchipr(base, read_gicd_dchipr(base) |
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(rt_owner << GICD_DCHIPR_RT_OWNER_SHIFT));
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/* Poll till PUP is zero to ensure write is complete */
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gicd_dchipr_wait_for_power_update_progress(base);
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}
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/*******************************************************************************
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* Configures the Chip Register to make connections to GICDs on
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* a multichip platform.
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******************************************************************************/
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static void set_gicd_chipr_n(uintptr_t base,
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unsigned int chip_id,
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uint64_t chip_addr,
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unsigned int spi_id_min,
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unsigned int spi_id_max)
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{
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unsigned int spi_block_min, spi_blocks;
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uint64_t chipr_n_val;
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/*
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* Ensure that group enables in GICD_CTLR are disabled and no pending
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* register writes to GICD_CTLR.
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*/
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if ((gicd_read_ctlr(base) &
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(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT |
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CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) {
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ERROR("GICD_CTLR group interrupts are either enabled or have "
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"pending writes. Cannot set CHIPR register.\n");
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panic();
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}
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/*
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* spi_id_min and spi_id_max of value 0 is used to intidicate that the
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* chip doesn't own any SPI block. Re-assign min and max values as SPI
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* id starts from 32.
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*/
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if (spi_id_min == 0 && spi_id_max == 0) {
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spi_id_min = GIC600_SPI_ID_MIN;
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spi_id_max = GIC600_SPI_ID_MIN;
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}
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spi_block_min = SPI_BLOCK_MIN_VALUE(spi_id_min);
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spi_blocks = SPI_BLOCKS_VALUE(spi_id_min, spi_id_max);
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chipr_n_val = (GICD_CHIPR_VALUE(chip_addr, spi_block_min, spi_blocks)) |
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GICD_CHIPRx_SOCKET_STATE;
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/*
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* Wait for DCHIPR.PUP to be zero before commencing writes to
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* GICD_CHIPRx.
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*/
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gicd_dchipr_wait_for_power_update_progress(base);
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/*
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* Assign chip addr, spi min block, number of spi blocks and bring chip
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* online by setting SocketState.
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*/
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write_gicd_chipr_n(base, chip_id, chipr_n_val);
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/*
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* Poll until DCHIP.PUP is zero to verify connection to rt_owner chip
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* is complete.
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*/
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gicd_dchipr_wait_for_power_update_progress(base);
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/*
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* Ensure that write to GICD_CHIPRx is successful and the chip_n came
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* online.
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*/
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if (read_gicd_chipr_n(base, chip_id) != chipr_n_val) {
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ERROR("GICD_CHIPR%u write failed\n", chip_id);
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panic();
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}
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/* Ensure that chip is in consistent state */
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if (((read_gicd_chipsr(base) & GICD_CHIPSR_RTS_MASK) >>
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GICD_CHIPSR_RTS_SHIFT) !=
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GICD_CHIPSR_RTS_STATE_CONSISTENT) {
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ERROR("Chip %u routing table is not in consistent state\n",
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chip_id);
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panic();
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}
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}
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/*******************************************************************************
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* Validates the GIC-600 Multichip data structure passed by the platform.
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******************************************************************************/
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static void gic600_multichip_validate_data(
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struct gic600_multichip_data *multichip_data)
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{
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unsigned int i, spi_id_min, spi_id_max, blocks_of_32;
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unsigned int multichip_spi_blocks = 0;
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assert(multichip_data != NULL);
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if (multichip_data->chip_count > GIC600_MAX_MULTICHIP) {
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ERROR("GIC-600 Multichip count should not exceed %d\n",
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GIC600_MAX_MULTICHIP);
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panic();
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}
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for (i = 0; i < multichip_data->chip_count; i++) {
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spi_id_min = multichip_data->spi_ids[i][SPI_MIN_INDEX];
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spi_id_max = multichip_data->spi_ids[i][SPI_MAX_INDEX];
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if ((spi_id_min != 0) || (spi_id_max != 0)) {
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/* SPI IDs range check */
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if (!(spi_id_min >= GIC600_SPI_ID_MIN) ||
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!(spi_id_max < GIC600_SPI_ID_MAX) ||
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!(spi_id_min <= spi_id_max) ||
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!((spi_id_max - spi_id_min + 1) % 32 == 0)) {
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ERROR("Invalid SPI IDs {%u, %u} passed for "
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"Chip %u\n", spi_id_min,
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spi_id_max, i);
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panic();
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}
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/* SPI IDs overlap check */
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blocks_of_32 = BLOCKS_OF_32(spi_id_min, spi_id_max);
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if ((multichip_spi_blocks & blocks_of_32) != 0) {
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ERROR("SPI IDs of Chip %u overlapping\n", i);
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panic();
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}
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multichip_spi_blocks |= blocks_of_32;
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}
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}
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}
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/*******************************************************************************
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* Intialize GIC-600 Multichip operation.
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******************************************************************************/
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void gic600_multichip_init(struct gic600_multichip_data *multichip_data)
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{
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unsigned int i;
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gic600_multichip_validate_data(multichip_data);
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INFO("GIC-600 Multichip driver is experimental\n");
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/*
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* Ensure that G0/G1S/G1NS interrupts are disabled. This also ensures
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* that GIC-600 Multichip configuration is done first.
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*/
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if ((gicd_read_ctlr(multichip_data->rt_owner_base) &
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(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT |
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CTLR_ENABLE_G1NS_BIT | GICD_CTLR_RWP_BIT)) != 0) {
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ERROR("GICD_CTLR group interrupts are either enabled or have "
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"pending writes.\n");
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panic();
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}
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/* Ensure that the routing table owner is in disconnected state */
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if (((read_gicd_chipsr(multichip_data->rt_owner_base) &
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GICD_CHIPSR_RTS_MASK) >> GICD_CHIPSR_RTS_SHIFT) !=
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GICD_CHIPSR_RTS_STATE_DISCONNECTED) {
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ERROR("GIC-600 routing table owner is not in disconnected "
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"state to begin multichip configuration\n");
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panic();
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}
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/* Initialize the GICD which is marked as routing table owner first */
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set_gicd_dchipr_rt_owner(multichip_data->rt_owner_base,
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multichip_data->rt_owner);
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set_gicd_chipr_n(multichip_data->rt_owner_base, multichip_data->rt_owner,
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multichip_data->chip_addrs[multichip_data->rt_owner],
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multichip_data->
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spi_ids[multichip_data->rt_owner][SPI_MIN_INDEX],
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multichip_data->
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spi_ids[multichip_data->rt_owner][SPI_MAX_INDEX]);
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for (i = 0; i < multichip_data->chip_count; i++) {
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if (i == multichip_data->rt_owner)
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continue;
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set_gicd_chipr_n(multichip_data->rt_owner_base, i,
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multichip_data->chip_addrs[i],
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multichip_data->spi_ids[i][SPI_MIN_INDEX],
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multichip_data->spi_ids[i][SPI_MAX_INDEX]);
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}
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}
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97
drivers/arm/gic/v3/gic600_multichip_private.h
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97
drivers/arm/gic/v3/gic600_multichip_private.h
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@ -0,0 +1,97 @@
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/*
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* Copyright (c) 2019, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GIC600_MULTICHIP_PRIVATE_H
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#define GIC600_MULTICHIP_PRIVATE_H
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#include <drivers/arm/gic600_multichip.h>
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#include "gicv3_private.h"
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/* GIC600 GICD multichip related offsets */
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#define GICD_CHIPSR U(0xC000)
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#define GICD_DCHIPR U(0xC004)
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#define GICD_CHIPR U(0xC008)
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/* GIC600 GICD multichip related masks */
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#define GICD_CHIPRx_PUP_BIT BIT_64(1)
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#define GICD_CHIPRx_SOCKET_STATE BIT_64(0)
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#define GICD_DCHIPR_PUP_BIT BIT_32(0)
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#define GICD_CHIPSR_RTS_MASK (BIT_32(4) | BIT_32(5))
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/* GIC600 GICD multichip related shifts */
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#define GICD_CHIPRx_ADDR_SHIFT 16
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#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10
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#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5
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#define GICD_CHIPSR_RTS_SHIFT 4
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#define GICD_DCHIPR_RT_OWNER_SHIFT 4
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#define GICD_CHIPSR_RTS_STATE_DISCONNECTED U(0)
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#define GICD_CHIPSR_RTS_STATE_UPDATING U(1)
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#define GICD_CHIPSR_RTS_STATE_CONSISTENT U(2)
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/* SPI interrupt id minimum and maximum range */
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#define GIC600_SPI_ID_MIN 32
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#define GIC600_SPI_ID_MAX 960
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/* Number of retries for PUP update */
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#define GICD_PUP_UPDATE_RETRIES 10000
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#define SPI_MIN_INDEX 0
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#define SPI_MAX_INDEX 1
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#define SPI_BLOCK_MIN_VALUE(spi_id_min) \
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(((spi_id_min) - GIC600_SPI_ID_MIN) / \
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GIC600_SPI_ID_MIN)
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#define SPI_BLOCKS_VALUE(spi_id_min, spi_id_max) \
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(((spi_id_max) - (spi_id_min) + 1) / \
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GIC600_SPI_ID_MIN)
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#define GICD_CHIPR_VALUE(chip_addr, spi_block_min, spi_blocks) \
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(((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \
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((spi_block_min) << GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT) | \
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((spi_blocks) << GICD_CHIPRx_SPI_BLOCKS_SHIFT))
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/*
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* Multichip data assertion macros
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*/
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/* Set bits from 0 to ((spi_id_max + 1) / 32) */
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#define SPI_BLOCKS_TILL_MAX(spi_id_max) ((1 << (((spi_id_max) + 1) >> 5)) - 1)
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/* Set bits from 0 to (spi_id_min / 32) */
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#define SPI_BLOCKS_TILL_MIN(spi_id_min) ((1 << ((spi_id_min) >> 5)) - 1)
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/* Set bits from (spi_id_min / 32) to ((spi_id_max + 1) / 32) */
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#define BLOCKS_OF_32(spi_id_min, spi_id_max) \
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SPI_BLOCKS_TILL_MAX(spi_id_max) ^ \
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SPI_BLOCKS_TILL_MIN(spi_id_min)
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/*******************************************************************************
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* GIC-600 multichip operation related helper functions
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******************************************************************************/
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static inline uint32_t read_gicd_dchipr(uintptr_t base)
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{
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return mmio_read_32(base + GICD_DCHIPR);
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}
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static inline uint64_t read_gicd_chipr_n(uintptr_t base, uint8_t n)
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{
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return mmio_read_64(base + (GICD_CHIPR + (8U * n)));
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}
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static inline uint32_t read_gicd_chipsr(uintptr_t base)
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{
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return mmio_read_32(base + GICD_CHIPSR);
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}
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static inline void write_gicd_dchipr(uintptr_t base, uint32_t val)
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{
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mmio_write_32(base + GICD_DCHIPR, val);
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}
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static inline void write_gicd_chipr_n(uintptr_t base, uint8_t n, uint64_t val)
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{
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mmio_write_64(base + (GICD_CHIPR + (8U * n)), val);
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}
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#endif /* GIC600_MULTICHIP_PRIVATE_H */
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55
include/drivers/arm/gic600_multichip.h
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55
include/drivers/arm/gic600_multichip.h
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@ -0,0 +1,55 @@
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/*
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* Copyright (c) 2019, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GIC600_MULTICHIP_H
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#define GIC600_MULTICHIP_H
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#include <stdint.h>
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/*
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* GIC-600 microarchitecture supports coherent multichip environments containing
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* up to 16 chips.
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*/
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#define GIC600_MAX_MULTICHIP 16
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/* SPI IDs array consist of min and max ids */
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#define GIC600_SPI_IDS_SIZE 2
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/*******************************************************************************
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* GIC-600 multichip data structure describes platform specific attributes
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* related to GIC-600 multichip. Platform port is expected to define these
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* attributes to initialize the multichip related registers and create
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* successful connections between the GIC-600s in a multichip system.
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*
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* The 'rt_owner_base' field contains the base address of the GIC Distributor
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* which owns the routing table.
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*
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* The 'rt_owner' field contains the chip number which owns the routing table.
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* Chip number or chip_id starts from 0.
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*
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* The 'chip_count' field contains the total number of chips in a multichip
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* system. This should match the number of entries in 'chip_addrs' and 'spi_ids'
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* fields.
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*
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* The 'chip_addrs' field contains array of chip addresses. These addresses are
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* implementation specific values.
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*
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* The 'spi_ids' field contains array of minimum and maximum SPI interrupt ids
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* that each chip owns. Note that SPI interrupt ids can range from 32 to 960 and
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* it should be group of 32 (i.e., SPI minimum and (SPI maximum + 1) should be
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* a multiple of 32). If a chip doesn't own any SPI interrupts a value of {0, 0}
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* should be passed.
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******************************************************************************/
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struct gic600_multichip_data {
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uintptr_t rt_owner_base;
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unsigned int rt_owner;
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unsigned int chip_count;
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uint64_t chip_addrs[GIC600_MAX_MULTICHIP];
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unsigned int spi_ids[GIC600_MAX_MULTICHIP][GIC600_SPI_IDS_SIZE];
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};
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void gic600_multichip_init(struct gic600_multichip_data *multichip_data);
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#endif /* GIC600_MULTICHIP_H */
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