Manish Pandey f2d6b4ee57 Neovers N1: added support to update presence of External LLC ... CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363		2020-01-27 14:44:35 +00:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	doc: Convert internal links to RST format	2019-10-08 15:58:03 +00:00
cpu-specific-build-macros.rst	Neovers N1: added support to update presence of External LLC	2020-01-27 14:44:35 +00:00
firmware-design.rst	bl31: Split into two separate memory regions	2019-12-29 12:00:40 -06:00
index.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
interrupt-framework-design.rst	doc: Convert internal links to RST format	2019-10-08 15:58:03 +00:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
trusted-board-boot-build.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
trusted-board-boot.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00