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279fedc1f8
The internal synchronisation timings of the FVP model version 11.0 build 11.0.34 and version 8.5 build 0.8.5202 has been changed compared to older version of the models. This change may have an impact on how the model behaves depending on the workload being run on the model. For example test failures have been seen where the primary core has powered on a secondary core but was then starved of host CPU time and so was not able to update power status, resulting a test failure due to an incorrect status. This, or similar behaviour, is not to be expected from real hardware platforms. This patch adds a usage note on how to launch these models so that internal synchronisation timing matches that of the older version of the models, specifically adding the -Q 100 option. Change-Id: If922afddba1581b7246ec889b3f1598533ea1b7e Signed-off-by: David Cunado <david.cunado@arm.com> |
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| .. | ||
| diagrams | ||
| plat | ||
| spd | ||
| arm-sip-service.rst | ||
| auth-framework.rst | ||
| change-log.rst | ||
| cpu-specific-build-macros.rst | ||
| firmware-design.rst | ||
| firmware-update.rst | ||
| interrupt-framework-design.rst | ||
| platform-migration-guide.rst | ||
| porting-guide.rst | ||
| psci-lib-integration-guide.rst | ||
| psci-pd-tree.rst | ||
| reset-design.rst | ||
| rt-svc-writers-guide.rst | ||
| trusted-board-boot.rst | ||
| user-guide.rst | ||
| xlat-tables-lib-v2-design.rst | ||