Kristina Martsenko 2af926ddd4 Initialize all translation table entries ... The current translation table code maps in a series of regions, zeroing the unmapped table entries before and in between the mapped regions. It doesn't, however, zero the unmapped entries after the last mapped region, leaving those entries at whatever value that memory has initially. This is bad because those values can look like valid translation table entries, pointing to valid physical addresses. The CPU is allowed to do speculative reads from any such addresses. If the addresses point to device memory, the results can be unpredictable. This patch zeroes the translation table entries following the last mapped region, ensuring all table entries are either valid or zero (invalid). In addition, it limits the value of ADDR_SPACE_SIZE to those allowed by the architecture and supported by the current code (see D4.2.5 in the Architecture Reference Manual). This simplifies this patch a lot and ensures existing code doesn't do unexpected things. Change-Id: Ic28b6c3f89d73ef58fa80319a9466bb2c7131c21		2016-03-07 09:13:34 +00:00
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aarch64	Initialize all translation table entries	2016-03-07 09:13:34 +00:00
cpus	Cortex-Axx: Unconditionally apply CPU reset operations	2016-02-08 09:31:18 +00:00
locks	Re-design bakery lock memory allocation and algorithm	2015-09-11 16:19:21 +01:00
semihosting	Fix bug in semihosting write function	2015-07-16 20:36:41 +01:00
stdlib	stdlib: add missing features to build PolarSSL	2015-01-28 18:26:59 +00:00