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2bf28e620a
The BL images share common stack management code which provides one coherent and one cacheable stack for every CPU. BL1 and BL2 just execute on the primary CPU during boot and do not require the additional CPU stacks. This patch provides separate stack support code for UP and MP images, substantially reducing the RAM usage for BL1 and BL2 for the FVP platform. This patch also provides macros for declaring stacks and calculating stack base addresses to improve consistency where this has to be done in the firmware. The stack allocation source files are now included via platform.mk rather than the common BLx makefiles. This allows each platform to select the appropriate MP/UP stack support for each BL image. Each platform makefile must be updated when including this commit. Fixes ARM-software/tf-issues#76 Change-Id: Ia251f61b8148ffa73eae3f3711f57b1ffebfa632
134 lines
3.9 KiB
ArmAsm
134 lines
3.9 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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.macro func_prologue
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stp x29, x30, [sp, #-0x10]!
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mov x29,sp
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.endm
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.macro func_epilogue
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ldp x29, x30, [sp], #0x10
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.endm
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.macro dcache_line_size reg, tmp
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mrs \tmp, ctr_el0
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ubfx \tmp, \tmp, #16, #4
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mov \reg, #4
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lsl \reg, \reg, \tmp
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.endm
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.macro icache_line_size reg, tmp
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mrs \tmp, ctr_el0
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and \tmp, \tmp, #0xf
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mov \reg, #4
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lsl \reg, \reg, \tmp
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.endm
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.macro smc_check label
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bl read_esr
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ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x0, #EC_AARCH64_SMC
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b.ne $label
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.endm
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.macro setup_dcsw_op_args start_level, end_level, clidr, shift, fw, ls
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mrs \clidr, clidr_el1
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mov \start_level, xzr
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ubfx \end_level, \clidr, \shift, \fw
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lsl \end_level, \end_level, \ls
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.endm
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/*
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* This macro verifies that the a given vector doesn't exceed the
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* architectural limit of 32 instructions. This is meant to be placed
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* immedately after the last instruction in the vector. It takes the
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* vector entry as the parameter
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*/
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.macro check_vector_size since
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.if (. - \since) > (32 * 4)
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.error "Vector exceeds 32 instructions"
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.endif
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.endm
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/*
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* This macro is used to create a function label and place the
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* code into a separate text section based on the function name
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* to enable elimination of unused code during linking
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*/
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.macro func _name
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.section .text.\_name, "ax"
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.type \_name, %function
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\_name:
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.endm
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/*
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* This macro declares an array of 1 or more stacks, properly
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* aligned and in the requested section
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*/
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#define STACK_ALIGN 6
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.macro declare_stack _name, _section, _size, _count
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.if ((\_size & ((1 << STACK_ALIGN) - 1)) <> 0)
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.error "Stack size not correctly aligned"
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.endif
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.section \_section, "aw", %nobits
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.align STACK_ALIGN
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\_name:
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.space ((\_count) * (\_size)), 0
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.endm
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/*
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* This macro calculates the base address of an MP stack using the
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* platform_get_core_pos() index, the name of the stack storage and
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* the size of each stack
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* In: X0 = MPIDR of CPU whose stack is wanted
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* Out: X0 = physical address of stack base
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* Clobber: X30, X1, X2
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*/
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.macro get_mp_stack _name, _size
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bl platform_get_core_pos
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ldr x2, =(\_name + \_size)
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mov x1, #\_size
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madd x0, x0, x1, x2
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.endm
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/*
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* This macro calculates the base address of a UP stack using the
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* name of the stack storage and the size of the stack
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* Out: X0 = physical address of stack base
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*/
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.macro get_up_stack _name, _size
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ldr x0, =(\_name + \_size)
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.endm
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