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https://github.com/CTCaer/switch-l4t-atf.git
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c3cf06f1a3
All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
111 lines
3.5 KiB
C
111 lines
3.5 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DW_UFS_H
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#define DW_UFS_H
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#include <stdint.h>
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/* Bus Throtting */
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#define BUSTHRTL 0xC0
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/* Outstanding OCP Requests */
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#define OOCPR 0xC4
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/* Fatal Error Interrupt Enable */
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#define FEIE 0xC8
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/* C-Port Direct Access Configuration register */
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#define CDACFG 0xD0
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/* C-Port Direct Access Transmit 1 register */
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#define CDATX1 0xD4
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/* C-Port Direct Access Transmit 2 register */
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#define CDATX2 0xD8
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/* C-Port Direct Access Receive 1 register */
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#define CDARX1 0xDC
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/* C-Port Direct Access Receive 2 register */
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#define CDARX2 0xE0
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/* C-Port Direct Access Status register */
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#define CDASTA 0xE4
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/* UPIU Loopback Configuration register */
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#define LBMCFG 0xF0
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/* UPIU Loopback Status */
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#define LBMSTA 0xF4
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/* Debug register */
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#define DBG 0xF8
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/* HClk Divider register */
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#define HCLKDIV 0xFC
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#define TX_HIBERN8TIME_CAP_OFFSET 0x000F
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#define TX_FSM_STATE_OFFSET 0x0041
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#define TX_FSM_STATE_LINE_RESET 7
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#define TX_FSM_STATE_LINE_CFG 6
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#define TX_FSM_STATE_HS_BURST 5
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#define TX_FSM_STATE_LS_BURST 4
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#define TX_FSM_STATE_STALL 3
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#define TX_FSM_STATE_SLEEP 2
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#define TX_FSM_STATE_HIBERN8 1
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#define TX_FSM_STATE_DISABLE 0
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#define RX_MIN_ACTIVATETIME_CAP_OFFSET 0x008F
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#define RX_HS_G2_SYNC_LENGTH_CAP_OFFSET 0x0094
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#define RX_HS_G3_SYNC_LENGTH_CAP_OFFSET 0x0095
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#define PA_AVAIL_TX_DATA_LANES_OFFSET 0x1520
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#define PA_TX_SKIP_OFFSET 0x155C
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#define PA_TX_SKIP_PERIOD_OFFSET 0x155D
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#define PA_LOCAL_TX_LCC_ENABLE_OFFSET 0x155E
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#define PA_ACTIVE_TX_DATA_LANES_OFFSET 0x1560
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#define PA_CONNECTED_TX_DATA_LANES_OFFSET 0x1561
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#define PA_TX_TRAILING_CLOCKS_OFFSET 0x1564
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#define PA_TX_GEAR_OFFSET 0x1568
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#define PA_TX_TERMINATION_OFFSET 0x1569
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#define PA_HS_SERIES_OFFSET 0x156A
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#define PA_PWR_MODE_OFFSET 0x1571
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#define PA_ACTIVE_RX_DATA_LANES_OFFSET 0x1580
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#define PA_CONNECTED_RX_DATA_LANES_OFFSET 0x1581
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#define PA_RX_PWR_STATUS_OFFSET 0x1582
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#define PA_RX_GEAR_OFFSET 0x1583
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#define PA_RX_TERMINATION_OFFSET 0x1584
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#define PA_SCRAMBLING_OFFSET 0x1585
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#define PA_MAX_RX_PWM_GEAR_OFFSET 0x1586
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#define PA_MAX_RX_HS_GEAR_OFFSET 0x1587
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#define PA_PACP_REQ_TIMEOUT_OFFSET 0x1590
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#define PA_PACP_REQ_EOB_TIMEOUT_OFFSET 0x1591
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#define PA_REMOTE_VER_INFO_OFFSET 0x15A0
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#define PA_LOGICAL_LANE_MAP_OFFSET 0x15A1
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#define PA_TACTIVATE_OFFSET 0x15A8
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#define PA_PWR_MODE_USER_DATA0_OFFSET 0x15B0
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#define PA_PWR_MODE_USER_DATA1_OFFSET 0x15B1
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#define PA_PWR_MODE_USER_DATA2_OFFSET 0x15B2
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#define PA_PWR_MODE_USER_DATA3_OFFSET 0x15B3
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#define PA_PWR_MODE_USER_DATA4_OFFSET 0x15B4
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#define PA_PWR_MODE_USER_DATA5_OFFSET 0x15B5
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#define DL_TC0_TX_FC_THRESHOLD_OFFSET 0x2040
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#define DL_AFC0_CREDIT_THRESHOLD_OFFSET 0x2044
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#define DL_TC0_OUT_ACK_THRESHOLD_OFFSET 0x2045
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#define DME_FC0_PROTECTION_TIMEOUT_OFFSET 0xD041
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#define DME_TC0_REPLAY_TIMEOUT_OFFSET 0xD042
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#define DME_AFC0_REQ_TIMEOUT_OFFSET 0xD043
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#define DME_FC1_PROTECTION_TIMEOUT_OFFSET 0xD044
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#define DME_TC1_REPLAY_TIMEOUT_OFFSET 0xD045
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#define DME_AFC1_REQ_TIMEOUT_OFFSET 0xD046
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#define VS_MPHY_CFG_UPDT_OFFSET 0xD085
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#define VS_MK2_EXTN_SUPPORT_OFFSET 0xD0AB
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#define VS_MPHY_DISABLE_OFFSET 0xD0C1
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#define VS_MPHY_DISABLE_MPHYDIS (1 << 0)
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typedef struct dw_ufs_params {
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uintptr_t reg_base;
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uintptr_t desc_base;
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size_t desc_size;
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unsigned long flags;
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} dw_ufs_params_t;
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int dw_ufs_init(dw_ufs_params_t *params);
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#endif /* DW_UFS_H */
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