mirror of
https://github.com/CTCaer/switch-l4t-atf.git
synced 2024-11-28 04:10:32 +00:00
ef93cfa3a2
This patch performs the following:
- Creating two corstone700 platforms under corstone700 board:
fvp and fpga
- Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform
- The platform can be specified using the TARGET_PLATFORM Makefile variable
(possible values are: fvp or fpga)
- Allowing to use u-boot by:
- Enabling NEED_BL33 option
- Fixing non-secure image base: For no preloaded bl33 we want to
have the NS base set on shared ram. Setup a memory map region
for NS in shared map and set the bl33 address in the area.
- Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected
platform
- Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY
Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
162 lines
3.4 KiB
Plaintext
162 lines
3.4 KiB
Plaintext
/*
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* Copyright (c) 2020, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "arm,Corstone-700";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0>;
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next-level-cache = <&L2_0>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x80000000>;
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};
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gic: interrupt-controller@1c000000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1c010000 0x1000>,
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<0x1c02f000 0x2000>,
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<0x1c04f000 0x1000>,
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<0x1c06f000 0x2000>;
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interrupts = <1 9 0xf08>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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smbclk: refclk24mhzx2 {
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/* Reference 24MHz clock x 2 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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clock-output-names = "smclk";
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};
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uartclk: uartclk {
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/* UART clock - 32MHz */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000000>;
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clock-output-names = "uartclk";
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};
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serial0: uart@1a510000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a510000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 19 4>;
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clocks = <&uartclk>, <&refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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serial1: uart@1a520000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x1a520000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <0 20 4>;
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clocks = <&uartclk>, <&refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xf08>,
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<1 14 0xf08>,
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<1 11 0xf08>,
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<1 10 0xf08>;
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};
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refclk: refclk@1a220000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x1a220000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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frame@1a230000 {
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frame-number = <0>;
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interrupts = <0 2 0xf04>;
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reg = <0x1a230000 0x1000>;
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};
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};
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mbox_es0mhu0: mhu@1b000000 {
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compatible = "arm,mhuv2","arm,primecell";
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reg = <0x1b000000 0x1000>,
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<0x1b010000 0x1000>;
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clocks = <&refclk100mhz>;
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clock-names = "apb_pclk";
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interrupts = <0 12 4>;
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interrupt-names = "mhu_rx";
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#mbox-cells = <1>;
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mbox-name = "arm-es0-mhu0";
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};
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mbox_es0mhu1: mhu@1b020000 {
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compatible = "arm,mhuv2","arm,primecell";
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reg = <0x1b020000 0x1000>,
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<0x1b030000 0x1000>;
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clocks = <&refclk100mhz>;
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clock-names = "apb_pclk";
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interrupts = <0 47 4>;
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interrupt-names = "mhu_rx";
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#mbox-cells = <1>;
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mbox-name = "arm-es0-mhu1";
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};
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mbox_semhu1: mhu@1b820000 {
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compatible = "arm,mhuv2","arm,primecell";
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reg = <0x1b820000 0x1000>,
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<0x1b830000 0x1000>;
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clocks = <&refclk100mhz>;
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clock-names = "apb_pclk";
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interrupts = <0 45 4>;
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interrupt-names = "mhu_rx";
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#mbox-cells = <1>;
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mbox-name = "arm-se-mhu1";
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};
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client {
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compatible = "arm,client";
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mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>;
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mbox-names = "es0mhu0", "es0mhu1", "semhu1";
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};
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extsys0: extsys@1A010310 {
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compatible = "arm,extsys_ctrl";
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reg = <0x1A010310 0x4>,
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<0x1A010314 0x4>;
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reg-names = "rstreg", "streg";
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};
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};
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