mirror of
https://github.com/CTCaer/switch-l4t-atf.git
synced 2024-12-02 23:56:35 +00:00
6563c0beb8
Most registers are 64-bit wide, even in AArch32 mode: - MAIR_ELx is equivalent to MAIR0 and MAIR1. - TTBR is 64 bit in both AArch64 and AArch32. The only difference is the TCR register, which is 32 bit in AArch32 and in EL3 in AArch64. For consistency with the rest of ELs in AArch64, it makes sense to also have it as a 64-bit value. Change-Id: I2274d66a28876702e7085df5f8aad0e7ec139da9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
||
|---|---|---|
| .. | ||
| aarch32 | ||
| aarch64 | ||
| compiler-rt | ||
| coreboot | ||
| cpus | ||
| el3_runtime | ||
| extensions | ||
| libfdt | ||
| locks | ||
| optee | ||
| pmf | ||
| psci | ||
| semihosting | ||
| stack_protector | ||
| stdlib | ||
| utils | ||
| xlat_tables | ||
| xlat_tables_v2 | ||
| zlib | ||