Arunachalam Ganapathy 68ac5ed049 fix(el3_runtime): fix SVE and AMU extension enablement flags ... If SVE are enabled for both Non-secure and Secure world along with AMU extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit from bl31. This restricts access to the AMU register set in normal world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT by saving and restoring CPTR_EL3 register from EL3 context. Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087		2021-07-23 10:33:59 +01:00
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arch	feat(sve): enable SVE for the secure world	2021-06-28 13:24:24 +01:00
bl1	Specify signed-ness of constants	2020-08-14 11:36:05 +00:00
bl2	BL2_AT_EL3: Enable pointer authentication support	2019-02-27 11:58:09 +00:00
bl2u	Standardise header guards across codebase	2018-11-08 10:20:19 +00:00
bl31	Use correct type when reading SCR register	2020-01-28 11:10:48 +00:00
bl32	spd: tlkd: support new TLK SMCs for RPMB service	2020-03-21 19:00:05 -07:00
common	feat(hw_crc): add support for HW computed CRC	2021-05-19 19:34:34 +01:00
drivers	feat(drivers/st): manage boot part in io_mmc	2021-06-04 10:08:39 +02:00
dt-bindings	refactor(dt-bindings): align irq bindings with kernel	2021-06-14 10:05:48 +02:00
export	Increase type widths to satisfy width requirements	2020-10-12 10:55:03 -05:00
lib	fix(el3_runtime): fix SVE and AMU extension enablement flags	2021-07-23 10:33:59 +01:00
plat	feat(plat/arm): enable PIE when RESET_TO_SP_MIN=1	2021-06-29 11:59:01 +01:00
services	Merge "feat(spmd): add support for FFA_SPM_ID_GET" into integration	2021-06-18 17:28:39 +02:00
tools_share	refactor(plat/arm): store UUID as a string, rather than ints	2021-04-28 12:13:58 +01:00