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597 lines
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ReStructuredText
Guide to migrate to new Platform porting interface
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==================================================
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.. section-numbering::
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:suffix: .
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.. contents::
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--------------
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Introduction
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------------
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The PSCI implementation in Trusted Firmware has undergone a redesign because of
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three requirements that the PSCI 1.0 specification introduced :
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- Removing the framework assumption about the structure of the MPIDR, and
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its relation to the power topology enables support for deeper and more
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complex hierarchies.
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- Reworking the power state coordination implementation in the framework
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to support the more detailed PSCI 1.0 requirements and reduce platform
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port complexity
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- Enable the use of the extended power\_state parameter and the larger StateID
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field
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The PSCI 1.0 implementation introduces new frameworks to fulfill the above
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requirements. These framework changes mean that the platform porting API must
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also be modified. This document is a guide to assist migration of the existing
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platform ports to the new platform API.
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This document describes the new platform API and compares it with the
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deprecated API. It also describes the compatibility layer that enables the
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existing platform ports to work with the PSCI 1.0 implementation. The
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deprecated platform API is documented for reference.
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Platform API modification due to PSCI framework changes
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-------------------------------------------------------
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This section describes changes to the platform APIs.
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Power domain topology framework platform API modifications
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----------------------------------------------------------
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This removes the assumption in the PSCI implementation that MPIDR
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based affinity instances map directly to power domains. A power domain, as
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described in section 4.2 of `PSCI`_, could contain a core or a logical group
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of cores (a cluster) which share some state on which power management
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operations can be performed. The existing affinity instance based APIs
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``plat_get_aff_count()`` and ``plat_get_aff_state()`` are deprecated. The new
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platform interfaces that are introduced for this framework are:
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- ``plat_core_pos_by_mpidr()``
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- ``plat_my_core_pos()``
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- ``plat_get_power_domain_tree_desc()``
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``plat_my_core_pos()`` and ``plat_core_pos_by_mpidr()`` are mandatory
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and are meant to replace the existing ``platform_get_core_pos()`` API.
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The description of these APIs can be found in the `Porting Guide`_.
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These are used by the power domain topology framework such that:
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#. The generic PSCI code does not generate MPIDRs or use them to query the
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platform about the number of power domains at a particular power level. The
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``plat_get_power_domain_tree_desc()`` provides a description of the power
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domain tree on the SoC through a pointer to the byte array containing the
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power domain topology tree description data structure.
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#. The linear indices returned by ``plat_core_pos_by_mpidr()`` and
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``plat_my_core_pos()`` are used to retrieve core power domain nodes from
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the power domain tree. These core indices are unique for a core and it is a
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number between ``0`` and ``PLATFORM_CORE_COUNT - 1``. The platform can choose
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to implement a static mapping between ``MPIDR`` and core index or implement
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a dynamic mapping, choosing to skip the unavailable/unused cores to compact
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the core indices.
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In addition, the platforms must define the macros ``PLAT_NUM_PWR_DOMAINS`` and
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``PLAT_MAX_PWR_LVL`` which replace the macros ``PLAT_NUM_AFFS`` and
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``PLATFORM_MAX_AFFLVL`` respectively. On platforms where the affinity instances
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correspond to power domains, the values of new macros remain the same as the
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old ones.
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More details on the power domain topology description and its platform
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interface can be found in `psci pd tree`_.
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Composite power state framework platform API modifications
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----------------------------------------------------------
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The state-ID field in the power-state parameter of a CPU\_SUSPEND call can be
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used to describe the composite power states specific to a platform. The existing
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PSCI state coordination had the limitation that it operates on a run/off
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granularity of power states and it did not interpret the state-ID field. This
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was acceptable as the specification requirement in PSCI 0.2 and the framework's
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approach to coordination only required maintaining a reference
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count of the number of cores that have requested the cluster to remain powered.
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In the PSCI 1.0 specification, this approach is non optimal. If composite
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power states are used, the PSCI implementation cannot make global
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decisions about state coordination required because it does not understand the
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platform specific states.
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The PSCI 1.0 implementation now defines a generic representation of the
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power-state parameter :
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.. code:: c
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typedef struct psci_power_state {
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plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1];
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} psci_power_state_t;
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``pwr_domain_state`` is an array where each index corresponds to a power level.
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Each entry in the array contains the local power state the power domain at
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that power level could enter. The meaning of the local power state value is
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platform defined, and can vary between levels in a single platform. The PSCI
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implementation constraints the values only so that it can classify the state
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as RUN, RETENTION or OFF as required by the specification:
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#. Zero means RUN
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#. All OFF state values at all levels must be higher than all
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RETENTION state values at all levels
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The platform is required to define the macros ``PLAT_MAX_RET_STATE`` and
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``PLAT_MAX_OFF_STATE`` to the framework. The requirement for these macros can
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be found in the `Porting Guide <porting-guide.rst>`__.
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The PSCI 1.0 implementation adds support to involve the platform in state
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coordination. This enables the platform to decide the final target state.
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During a request to place a power domain in a low power state, the platform
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is passed an array of requested ``plat_local_state_t`` for that power domain by
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each core within it through the ``plat_get_target_pwr_state()`` API. This API
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coordinates amongst these requested states to determine a target
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``plat_local_state_t`` for that power domain. A default weak implementation of
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this API is provided in the platform layer which returns the minimum of the
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requested local states back to the PSCI state coordination. More details
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of ``plat_get_target_pwr_state()`` API can be found in the
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`Porting Guide <porting-guide.rst#user-content-function--plat_get_target_pwr_state-optional>`__.
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The PSCI Generic implementation expects platform ports to populate the handlers
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for the ``plat_psci_ops`` structure which is declared as :
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.. code:: c
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typedef struct plat_psci_ops {
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void (*cpu_standby)(plat_local_state_t cpu_state);
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int (*pwr_domain_on)(u_register_t mpidr);
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void (*pwr_domain_off)(const psci_power_state_t *target_state);
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void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
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void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
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void (*pwr_domain_suspend_finish)(
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const psci_power_state_t *target_state);
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void (*system_off)(void) __dead2;
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void (*system_reset)(void) __dead2;
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int (*validate_power_state)(unsigned int power_state,
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psci_power_state_t *req_state);
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int (*validate_ns_entrypoint)(unsigned long ns_entrypoint);
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void (*get_sys_suspend_power_state)(
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psci_power_state_t *req_state);
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} plat_psci_ops_t;
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The description of these handlers can be found in the `Porting Guide <porting-guide.rst#user-content-function--plat_setup_psci_ops-mandatory>`__.
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The previous ``plat_pm_ops`` structure is deprecated. Compared with the previous
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handlers, the major differences are:
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- Difference in parameters
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The PSCI 1.0 implementation depends on the ``validate_power_state`` handler to
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convert the power-state parameter (possibly encoding a composite power state)
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passed in a PSCI ``CPU_SUSPEND`` to the ``psci_power_state`` format. This handler
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is now mandatory for PSCI ``CPU_SUSPEND`` support.
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The ``plat_psci_ops`` handlers, ``pwr_domain_off`` and ``pwr_domain_suspend``, are
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passed the target local state for each affected power domain. The platform
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must execute operations specific to these target states. Similarly,
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``pwr_domain_on_finish`` and ``pwr_domain_suspend_finish`` are passed the local
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states of the affected power domains before wakeup. The platform
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must execute actions to restore these power domains from these specific
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local states.
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- Difference in invocation
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Whereas the power management handlers in ``plat_pm_ops`` used to be invoked
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for each affinity level till the target affinity level, the new handlers
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are only invoked once. The ``target_state`` encodes the target low power
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state or the low power state woken up from for each affected power domain.
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- Difference in semantics
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Although the previous ``suspend`` handlers could be used for power down as well
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as retention at different affinity levels, the new handlers make this support
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explicit. The ``pwr_domain_suspend`` can be used to specify powerdown and
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retention at various power domain levels subject to the conditions mentioned
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in section 4.2.1 of `PSCI`_
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Unlike the previous ``standby`` handler, the ``cpu_standby()`` handler is only used
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as a fast path for placing a core power domain into a standby or retention
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state.
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The below diagram shows the sequence of a PSCI SUSPEND call and the interaction
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with the platform layer depicting the exchange of data between PSCI Generic
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layer and the platform layer.
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|Image 1|
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Refer `plat/arm/board/fvp/fvp\_pm.c`_ for the implementation details of
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these handlers for the FVP. The commit `38dce70f51fb83b27958ba3e2ad15f5635cb1061`_
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demonstrates the migration of ARM reference platforms to the new platform API.
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Miscellaneous modifications
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---------------------------
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In addition to the framework changes, unification of warm reset entry points on
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wakeup from low power modes has led to a change in the platform API. In the
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earlier implementation, the warm reset entry used to be programmed into the
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mailboxes by the 'ON' and 'SUSPEND' power management hooks. In the PSCI 1.0
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implementation, this information is not required, because it can figure that
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out by querying affinity info state whether to execute the 'suspend\_finisher\`
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or 'on\_finisher'.
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As a result, the warm reset entry point must be programmed only once. The
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``plat_setup_psci_ops()`` API takes the secure entry point as an
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additional parameter to enable the platforms to configure their mailbox. The
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plat\_psci\_ops handlers ``pwr_domain_on`` and ``pwr_domain_suspend`` no longer take
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the warm reset entry point as a parameter.
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Also, some platform APIs which took ``MPIDR`` as an argument were only ever
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invoked to perform actions specific to the caller core which makes the argument
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redundant. Therefore the platform APIs ``plat_get_my_entrypoint()``,
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``plat_is_my_cpu_primary()``, ``plat_set_my_stack()`` and
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``plat_get_my_stack()`` are defined which are meant to be invoked only for
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operations on the current caller core instead of ``platform_get_entrypoint()``,
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``platform_is_primary_cpu()``, ``platform_set_stack()`` and ``platform_get_stack()``.
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Compatibility layer
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-------------------
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To ease the migration of the platform ports to the new porting interface,
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a compatibility layer is introduced that essentially implements a glue layer
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between the old platform API and the new API. The build flag
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``ENABLE_PLAT_COMPAT`` (enabled by default), specifies whether to enable this
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layer or not. A platform port which has migrated to the new API can disable
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this flag within the platform specific makefile.
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The compatibility layer works on the assumption that the onus of
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state coordination, in case multiple low power states are supported,
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is with the platform. The generic PSCI implementation only takes into
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account whether the suspend request is power down or not. This corresponds
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with the behavior of the PSCI implementation before the introduction of
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new frameworks. Also, it assumes that the affinity levels of the platform
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correspond directly to the power domain levels.
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The compatibility layer dynamically constructs the new topology
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description array by querying the platform using ``plat_get_aff_count()``
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and ``plat_get_aff_state()`` APIs. The linear index returned by
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``platform_get_core_pos()`` is used as the core index for the cores. The
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higher level (non-core) power domain nodes must know the cores contained
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within its domain. It does so by storing the core index of first core
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within it and number of core indexes following it. This means that core
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indices returned by ``platform_get_core_pos()`` for cores within a particular
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power domain must be consecutive. We expect that this is the case for most
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platform ports including ARM reference platforms.
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The old PSCI helpers like ``psci_get_suspend_powerstate()``,
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``psci_get_suspend_stateid()``, ``psci_get_suspend_stateid_by_mpidr()``,
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``psci_get_max_phys_off_afflvl()`` and ``psci_get_suspend_afflvl()`` are also
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implemented for the compatibility layer. This allows the existing
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platform ports to work with the new PSCI frameworks without significant
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rework.
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Deprecated Platform API
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-----------------------
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This section documents the deprecated platform porting API.
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Common mandatory modifications
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------------------------------
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The mandatory macros to be defined by the platform port in ``platform_def.h``
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- **#define : PLATFORM\_NUM\_AFFS**
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Defines the total number of nodes in the affinity hierarchy at all affinity
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levels used by the platform.
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- **#define : PLATFORM\_MAX\_AFFLVL**
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Defines the maximum affinity level that the power management operations
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should apply to. ARMv8-A has support for four affinity levels. It is likely
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that hardware will implement fewer affinity levels. This macro allows the
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PSCI implementation to consider only those affinity levels in the system
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that the platform implements. For example, the Base AEM FVP implements two
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clusters with a configurable number of cores. It reports the maximum
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affinity level as 1, resulting in PSCI power control up to the cluster
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level.
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The following functions must be implemented by the platform port to enable
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the reset vector code to perform the required tasks.
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Function : platform\_get\_entrypoint() [mandatory]
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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::
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Argument : unsigned long
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Return : unsigned long
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This function is called with the ``SCTLR.M`` and ``SCTLR.C`` bits disabled. The core
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is identified by its ``MPIDR``, which is passed as the argument. The function is
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responsible for distinguishing between a warm and cold reset using platform-
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specific means. If it is a warm reset, it returns the entrypoint into the
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BL31 image that the core must jump to. If it is a cold reset, this function
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must return zero.
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This function is also responsible for implementing a platform-specific mechanism
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to handle the condition where the core has been warm reset but there is no
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entrypoint to jump to.
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This function does not follow the Procedure Call Standard used by the
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Application Binary Interface for the ARM 64-bit architecture. The caller should
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not assume that callee saved registers are preserved across a call to this
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function.
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Function : platform\_is\_primary\_cpu() [mandatory]
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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::
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Argument : unsigned long
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Return : unsigned int
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This function identifies a core by its ``MPIDR``, which is passed as the argument,
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to determine whether this core is the primary core or a secondary core. A return
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value of zero indicates that the core is not the primary core, while a non-zero
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return value indicates that the core is the primary core.
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Common optional modifications
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-----------------------------
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Function : platform\_get\_core\_pos()
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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::
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Argument : unsigned long
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Return : int
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A platform may need to convert the ``MPIDR`` of a core to an absolute number, which
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can be used as a core-specific linear index into blocks of memory (for example
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while allocating per-core stacks). This routine contains a simple mechanism
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to perform this conversion, using the assumption that each cluster contains a
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maximum of four cores:
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::
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linear index = cpu_id + (cluster_id * 4)
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cpu_id = 8-bit value in MPIDR at affinity level 0
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cluster_id = 8-bit value in MPIDR at affinity level 1
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Function : platform\_set\_stack()
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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::
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Argument : unsigned long
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Return : void
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This function sets the current stack pointer to the normal memory stack that
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has been allocated for the core specified by MPIDR. For BL images that only
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require a stack for the primary core the parameter is ignored. The size of
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the stack allocated to each core is specified by the platform defined constant
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``PLATFORM_STACK_SIZE``.
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Common implementations of this function for the UP and MP BL images are
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provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
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`plat/common/aarch64/platform\_mp\_stack.S`_
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Function : platform\_get\_stack()
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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::
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Argument : unsigned long
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Return : unsigned long
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This function returns the base address of the normal memory stack that
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has been allocated for the core specificed by MPIDR. For BL images that only
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require a stack for the primary core the parameter is ignored. The size of
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the stack allocated to each core is specified by the platform defined constant
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``PLATFORM_STACK_SIZE``.
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Common implementations of this function for the UP and MP BL images are
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provided in `plat/common/aarch64/platform\_up\_stack.S`_ and
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`plat/common/aarch64/platform\_mp\_stack.S`_
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Modifications for Power State Coordination Interface (in BL31)
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--------------------------------------------------------------
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The following functions must be implemented to initialize PSCI functionality in
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the ARM Trusted Firmware.
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Function : plat\_get\_aff\_count() [mandatory]
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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::
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Argument : unsigned int, unsigned long
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Return : unsigned int
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This function may execute with the MMU and data caches enabled if the platform
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port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
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called by the primary core.
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This function is called by the PSCI initialization code to detect the system
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topology. Its purpose is to return the number of affinity instances implemented
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at a given ``affinity level`` (specified by the first argument) and a given
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``MPIDR`` (specified by the second argument). For example, on a dual-cluster
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system where first cluster implements two cores and the second cluster
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implements four cores, a call to this function with an ``MPIDR`` corresponding
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to the first cluster (``0x0``) and affinity level 0, would return 2. A call
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to this function with an ``MPIDR`` corresponding to the second cluster (``0x100``)
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and affinity level 0, would return 4.
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Function : plat\_get\_aff\_state() [mandatory]
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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::
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Argument : unsigned int, unsigned long
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Return : unsigned int
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This function may execute with the MMU and data caches enabled if the platform
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port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
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called by the primary core.
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This function is called by the PSCI initialization code. Its purpose is to
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return the state of an affinity instance. The affinity instance is determined by
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the affinity ID at a given ``affinity level`` (specified by the first argument)
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and an ``MPIDR`` (specified by the second argument). The state can be one of
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``PSCI_AFF_PRESENT`` or ``PSCI_AFF_ABSENT``. The latter state is used to cater for
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system topologies where certain affinity instances are unimplemented. For
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example, consider a platform that implements a single cluster with four cores and
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another core implemented directly on the interconnect with the cluster. The
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``MPIDR``\ s of the cluster would range from ``0x0-0x3``. The ``MPIDR`` of the single
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core is 0x100 to indicate that it does not belong to cluster 0. Cluster 1
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is missing but needs to be accounted for to reach this single core in the
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topology tree. Therefore it is marked as ``PSCI_AFF_ABSENT``.
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Function : platform\_setup\_pm() [mandatory]
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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::
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Argument : const plat_pm_ops **
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Return : int
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This function may execute with the MMU and data caches enabled if the platform
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port does the necessary initializations in ``bl31_plat_arch_setup()``. It is only
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called by the primary core.
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This function is called by PSCI initialization code. Its purpose is to export
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handler routines for platform-specific power management actions by populating
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the passed pointer with a pointer to the private ``plat_pm_ops`` structure of
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BL31.
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A description of each member of this structure is given below. A platform port
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is expected to implement these handlers if the corresponding PSCI operation
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is to be supported and these handlers are expected to succeed if the return
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type is ``void``.
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plat\_pm\_ops.affinst\_standby()
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Perform the platform-specific setup to enter the standby state indicated by the
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passed argument. The generic code expects the handler to succeed.
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plat\_pm\_ops.affinst\_on()
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^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Perform the platform specific setup to power on an affinity instance, specified
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by the ``MPIDR`` (first argument) and ``affinity level`` (third argument). The
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``state`` (fourth argument) contains the current state of that affinity instance
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(ON or OFF). This is useful to determine whether any action must be taken. For
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example, while powering on a core, the cluster that contains this core might
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already be in the ON state. The platform decides what actions must be taken to
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transition from the current state to the target state (indicated by the power
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management operation). The generic code expects the platform to return
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E\_SUCCESS on success or E\_INTERN\_FAIL for any failure.
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plat\_pm\_ops.affinst\_off()
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Perform the platform specific setup to power off an affinity instance of the
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calling core. It is called by the PSCI ``CPU_OFF`` API implementation.
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The ``affinity level`` (first argument) and ``state`` (second argument) have
|
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a similar meaning as described in the ``affinst_on()`` operation. They
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identify the affinity instance on which the call is made and its
|
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current state. This gives the platform port an indication of the
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state transition it must make to perform the requested action. For example, if
|
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the calling core is the last powered on core in the cluster, after powering down
|
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affinity level 0 (the core), the platform port should power down affinity
|
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level 1 (the cluster) as well. The generic code expects the handler to succeed.
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plat\_pm\_ops.affinst\_suspend()
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Perform the platform specific setup to power off an affinity instance of the
|
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calling core. It is called by the PSCI ``CPU_SUSPEND`` API and ``SYSTEM_SUSPEND``
|
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API implementation
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The ``affinity level`` (second argument) and ``state`` (third argument) have a
|
|
similar meaning as described in the ``affinst_on()`` operation. They are used to
|
|
identify the affinity instance on which the call is made and its current state.
|
|
This gives the platform port an indication of the state transition it must
|
|
make to perform the requested action. For example, if the calling core is the
|
|
last powered on core in the cluster, after powering down affinity level 0
|
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(the core), the platform port should power down affinity level 1 (the cluster)
|
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as well.
|
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The difference between turning an affinity instance off and suspending it
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is that in the former case, the affinity instance is expected to re-initialize
|
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its state when it is next powered on (see ``affinst_on_finish()``). In the latter
|
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case, the affinity instance is expected to save enough state so that it can
|
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resume execution by restoring this state when it is powered on (see
|
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``affinst_suspend_finish()``).The generic code expects the handler to succeed.
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plat\_pm\_ops.affinst\_on\_finish()
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This function is called by the PSCI implementation after the calling core is
|
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powered on and released from reset in response to an earlier PSCI ``CPU_ON`` call.
|
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It performs the platform-specific setup required to initialize enough state for
|
|
this core to enter the Normal world and also provide secure runtime firmware
|
|
services.
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The ``affinity level`` (first argument) and ``state`` (second argument) have a
|
|
similar meaning as described in the previous operations. The generic code
|
|
expects the handler to succeed.
|
|
|
|
plat\_pm\_ops.affinst\_suspend\_finish()
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
This function is called by the PSCI implementation after the calling core is
|
|
powered on and released from reset in response to an asynchronous wakeup
|
|
event, for example a timer interrupt that was programmed by the core during the
|
|
``CPU_SUSPEND`` call or ``SYSTEM_SUSPEND`` call. It performs the platform-specific
|
|
setup required to restore the saved state for this core to resume execution
|
|
in the Normal world and also provide secure runtime firmware services.
|
|
|
|
The ``affinity level`` (first argument) and ``state`` (second argument) have a
|
|
similar meaning as described in the previous operations. The generic code
|
|
expects the platform to succeed.
|
|
|
|
plat\_pm\_ops.validate\_power\_state()
|
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
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This function is called by the PSCI implementation during the ``CPU_SUSPEND``
|
|
call to validate the ``power_state`` parameter of the PSCI API. If the
|
|
``power_state`` is known to be invalid, the platform must return
|
|
PSCI\_E\_INVALID\_PARAMS as an error, which is propagated back to the Normal
|
|
world PSCI client.
|
|
|
|
plat\_pm\_ops.validate\_ns\_entrypoint()
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
This function is called by the PSCI implementation during the ``CPU_SUSPEND``,
|
|
``SYSTEM_SUSPEND`` and ``CPU_ON`` calls to validate the Non-secure ``entry_point``
|
|
parameter passed by the Normal world. If the ``entry_point`` is known to be
|
|
invalid, the platform must return PSCI\_E\_INVALID\_PARAMS as an error, which is
|
|
propagated back to the Normal world PSCI client.
|
|
|
|
plat\_pm\_ops.get\_sys\_suspend\_power\_state()
|
|
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
|
|
|
This function is called by the PSCI implementation during the ``SYSTEM_SUSPEND``
|
|
call to return the ``power_state`` parameter. This allows the platform to encode
|
|
the appropriate State-ID field within the ``power_state`` parameter which can be
|
|
utilized in ``affinst_suspend()`` to suspend to system affinity level. The
|
|
``power_state`` parameter should be in the same format as specified by the
|
|
PSCI specification for the CPU\_SUSPEND API.
|
|
|
|
--------------
|
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|
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*Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.*
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.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
|
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.. _Porting Guide: porting-guide.rst#user-content-function--plat_my_core_pos
|
|
.. _psci pd tree: psci-pd-tree.rst
|
|
.. _plat/arm/board/fvp/fvp\_pm.c: ../plat/arm/board/fvp/fvp_pm.c
|
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.. _38dce70f51fb83b27958ba3e2ad15f5635cb1061: https://github.com/ARM-software/arm-trusted-firmware/commit/38dce70f51fb83b27958ba3e2ad15f5635cb1061
|
|
.. _plat/common/aarch64/platform\_up\_stack.S: ../plat/common/aarch64/platform_up_stack.S
|
|
.. _plat/common/aarch64/platform\_mp\_stack.S: ../plat/common/aarch64/platform_mp_stack.S
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.. |Image 1| image:: diagrams/psci-suspend-sequence.png?raw=true
|