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This change makes AMU auxiliary counters configurable on a per-core basis, controlled by `ENABLE_AMU_AUXILIARY_COUNTERS`. Auxiliary counters can be described via the `HW_CONFIG` device tree if the `ENABLE_AMU_FCONF` build option is enabled, or the platform must otherwise implement the `plat_amu_topology` function. A new phandle property for `cpu` nodes (`amu`) has been introduced to the `HW_CONFIG` specification to allow CPUs to describe the view of their own AMU: ``` cpu0: cpu@0 { ... amu = <&cpu0_amu>; }; ``` Multiple cores may share an `amu` handle if they implement the same set of auxiliary counters. AMU counters are described for one or more AMUs through the use of a new `amus` node: ``` amus { cpu0_amu: amu-0 { #address-cells = <1>; #size-cells = <0>; counter@0 { reg = <0>; enable-at-el3; }; counter@n { reg = <n>; ... }; }; }; ``` This structure describes the **auxiliary** (group 1) AMU counters. Architected counters have architecturally-defined behaviour, and as such do not require DTB entries. These `counter` nodes support two properties: - The `reg` property represents the counter register index. - The presence of the `enable-at-el3` property determines whether the firmware should enable the counter prior to exiting EL3. Change-Id: Ie43aee010518c5725a3b338a4899b0857caf4c28 Signed-off-by: Chris Kay <chris.kay@arm.com> |
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readme.rst |
Trusted Firmware-A ================== Trusted Firmware-A (TF-A) is a reference implementation of secure world software for `Arm A-Profile architectures`_ (Armv8-A and Armv7-A), including an Exception Level 3 (EL3) `Secure Monitor`_. It provides a suitable starting point for productization of secure world boot and runtime firmware, in either the AArch32 or AArch64 execution states. TF-A implements Arm interface standards, including: - `Power State Coordination Interface (PSCI)`_ - `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT)`_ - `SMC Calling Convention`_ - `System Control and Management Interface (SCMI)`_ - `Software Delegated Exception Interface (SDEI)`_ The code is designed to be portable and reusable across hardware platforms and software models that are based on the Armv8-A and Armv7-A architectures. In collaboration with interested parties, we will continue to enhance TF-A with reference implementations of Arm standards to benefit developers working with Armv7-A and Armv8-A TrustZone technology. Users are encouraged to do their own security validation, including penetration testing, on any secure world code derived from TF-A. More Info and Documentation --------------------------- To find out more about Trusted Firmware-A, please `view the full documentation`_ that is available through `trustedfirmware.org`_. -------------- *Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.* .. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile .. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php .. _Power State Coordination Interface (PSCI): PSCI_ .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf .. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a .. _SMC Calling Convention: http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf .. _System Control and Management Interface (SCMI): SCMI_ .. _SCMI: http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf .. _Software Delegated Exception Interface (SDEI): SDEI_ .. _SDEI: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf .. _Arm A-Profile architectures: https://developer.arm.com/architectures/cpu-architecture/a-profile .. _view the full documentation: https://www.trustedfirmware.org/docs/tf-a .. _trustedfirmware.org: http://www.trustedfirmware.org