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https://github.com/CTCaer/switch-l4t-atf.git
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0063dd1708
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented as well, it is possible to control whether PMU counters take into account events happening on other threads. If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit leaving it to effective state of 0 regardless of any write to it. This patch introduces the DISABLE_MTPMU flag, which allows to diable multithread event count from EL3 (or EL2). The flag is disabled by default so the behavior is consistent with those architectures that do not implement FEAT_MTPMU. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
38 lines
893 B
Makefile
38 lines
893 B
Makefile
#
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# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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BL2_SOURCES += bl2/bl2_image_load_v2.c \
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bl2/bl2_main.c \
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bl2/${ARCH}/bl2_arch_setup.c \
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lib/locks/exclusive/${ARCH}/spinlock.S \
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plat/common/${ARCH}/platform_up_stack.S \
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${MBEDTLS_SOURCES}
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ifeq (${ARCH},aarch64)
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BL2_SOURCES += common/aarch64/early_exceptions.S
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endif
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ifeq (${BL2_AT_EL3},0)
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BL2_SOURCES += bl2/${ARCH}/bl2_entrypoint.S
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BL2_LINKERFILE := bl2/bl2.ld.S
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else
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BL2_SOURCES += bl2/${ARCH}/bl2_el3_entrypoint.S \
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bl2/${ARCH}/bl2_el3_exceptions.S \
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lib/cpus/${ARCH}/cpu_helpers.S \
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lib/cpus/errata_report.c
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ifeq (${DISABLE_MTPMU},1)
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BL2_SOURCES += lib/extensions/mtpmu/${ARCH}/mtpmu.S
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endif
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ifeq (${ARCH},aarch64)
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BL2_SOURCES += lib/cpus/aarch64/dsu_helpers.S
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endif
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BL2_LINKERFILE := bl2/bl2_el3.ld.S
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endif
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