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1bdbdc3b3f
In contrast with the non-multi-threading DTS, this enumerates MPIDR values shifted by one affinity level to the left. The newly added DTS reflects CPUs with a single thread in them. Since both DTS files are the same apart from MPIDR contents, the common bits have been moved to a separate file that's then included from the top-level DTS files. The multi-threading version only updates the MPIDR contents. Change-Id: Id225cd93574f764171df8962ac76f42fcb6bba4b Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
42 lines
443 B
Plaintext
42 lines
443 B
Plaintext
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/include/ "fvp-base-gicv3-psci-common.dtsi"
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&CPU0 {
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reg = <0x0 0x0>;
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};
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&CPU1 {
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reg = <0x0 0x100>;
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};
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&CPU2 {
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reg = <0x0 0x200>;
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};
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&CPU3 {
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reg = <0x0 0x300>;
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};
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&CPU4 {
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reg = <0x0 0x10000>;
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};
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&CPU5 {
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reg = <0x0 0x10100>;
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};
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&CPU6 {
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reg = <0x0 0x10200>;
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};
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&CPU7 {
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reg = <0x0 0x10300>;
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};
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