mirror of
https://github.com/CTCaer/switch-l4t-atf.git
synced 2025-03-03 16:08:31 +00:00
0ad5b318f7
DynamIQ based designs have upto 8 CPUs in each cluster. This patch fixes the device tree node which describes the topology of the CPU for DynamIQ FVP Model. Change-Id: I7146bc79029ce38314026d4853e5b6406863725c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
41 lines
537 B
Plaintext
41 lines
537 B
Plaintext
/*
|
|
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "fvp-base-gicv3-psci-common.dtsi"
|
|
|
|
/* DynamIQ based designs have upto 8 CPUs in each cluster */
|
|
|
|
&CPU_MAP {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&CPU0>;
|
|
};
|
|
core1 {
|
|
cpu = <&CPU1>;
|
|
};
|
|
core2 {
|
|
cpu = <&CPU2>;
|
|
};
|
|
core3 {
|
|
cpu = <&CPU3>;
|
|
};
|
|
core4 {
|
|
cpu = <&CPU4>;
|
|
};
|
|
core5 {
|
|
cpu = <&CPU5>;
|
|
};
|
|
core6 {
|
|
cpu = <&CPU6>;
|
|
};
|
|
core7 {
|
|
cpu = <&CPU7>;
|
|
};
|
|
};
|
|
};
|